IBM PowerPC 405GP

Ie EDE UDE IA2 DW1 DW2 IA3 MRR
* * ~ * * * *
1
0
11 1213141516171819110111112113114
t t t t t t t
*
21122 23124
31
1
BT TIE IA1 DR1 DR2 IDE 1M
Figure 12-6. Debug Status Register (OBSR)
0 IC Instruction Completion Debug Event
o Event did not occur
1 Event occurred
1
BT Branch Taken Debug Event
o Event did not occur
1 Event occurred
2 EDE
Exception Debug Event
o Event did not occur
1 Event occurred
3
TIE Trap Instruction Debug Event
o Event did not occur
1 Event occurred
4
UDE Unconditional Debug Event
o Event did not occur
1 Event occurred
5
IA1 IAC1 Debug Event
o Event did not occur
1 Event occurred
6
IA2 IAC2 Debug Event
o Event did not occur
1 Event occurred
7
DR1 DAC1 Read Debug Event
o Event did not occur
1 Event occurred
8
DW1 DAC1 Write Debug Event
o Event did not occur
1 Event occurred
9 DR2
DAC2 Read Debug Event
o Event did not occur
1 Event occurred
10 DW2 DAC2 Write Debug Event
o Event did not occur
1 Event occurred
Preliminary
Debugging
12-13