13.1.1 CPM Enable Register (CPCO_ER)
The CPCO_ER bits enable the process of putting a functional unit to sleep. The class of a unit
determines how its interface
signals are controlled when the bit associated with the unit is set to
1.
Class
1
Class
2
Class
3
When an associated
CPCO_ER bit is set to
1,
the CPM_Sleep_N signal to the class
1 unit is asserted. When the bit is set to
0,
CPM_Sleep_N is deasserted. There are
some
additional considerations to avoid generating extraneous interrupts when
waking the
UIC. Before enabling sleep mode (setting DPCO_ER[UIC] to 1), save the
contents of the
UIC Masked Status Register (UIC_MSR) and UIC Enable Register
(UICO_ER), and disable all interrupts by setting UICO_ER to
0.
After exiting sleep
mode, write the ones complement of the saved contents of the UIC_MSR to the UIC
Status Register (UICO_SR), and restore the state of the UICO_ER.
When an associated CPCO_ER bit is set to
1,
and the Sleep_Req signal from the
class 2 unit is asserted (the unit is requesting sleep state), CPM_Sleep_N to the
class 2 unit is asserted. When the bit is set to
0,
the CPM_Sleep_N signal is
deasserted.
When an associated
CPCO_ER bit is set to
1,
the CPM_Sleeplnit signal to the class
3 unit is asserted (the CPM controller is requesting permission
to
put the unit to
sleep). When the class 3 unit activating the Sleep_Req
in
response, (the unit is
giving permission to be put to
sleep), CPM_Sleep_N signal to the class 3 unit is
asserted. When the bit is set to
0,
CPM_Sleeplnit and CPM_Sleep_N are
deasserted.
13.1.2 CPM Force Register (CPCO_FR)
Setting a CPCO_FR bit forces assertion of the CPM_Sleep_N signal to the functional unit. For a class
1 unit, this is equivalent to setting the CPCO_ER bit associated with the unit. For class 2
or
class 3·
units, CPM_Sleep_N is asserted regardless of the state of the Sleep_Req signal coming from the
unit.
13.1.3 CPM Status Register (CPCO_SR)
The read-only CPCO_SR shows the current state of all CPM_Sleep_N signals.
Preliminary Clock and Power Management 13-3
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