IBM PowerPC 405GP

Figure 17-57. Bridge Options 2 Register (PCICO_BRDGOPT2) ................................................................. 17-52
Figure 17-58.
Power Management State Change Request Register (PCICO_PMSCRR) .......................... 17-54
Figure 17-60.
PCI Master Burst Read From SDRAM ................................................................................. 17-68
Figure 17-61.
PCI Master Burst Write To SDRAM ...................................................................................... 17-72
Figure 17-62.
CPU Read From PCI Memory Slave, Nonprefetching .......................................................... 17-76
Figure 17-63.
CPU Read From PCI Memory Slave, Prefetching ................................................................ 17-78
Figure 17-64.
CPU Write To PCI Memory Slave ........................................................................................ 17-82
Figure 17-65.
PCI Memory To SDRAM DMA Transfer ............................................................................... 17-86
Figure 17-66. SDRAM To
PCI Memory DMA Transfer ............................................................................... 17-88
Figure 17-67.
PCI Master Burst Read From SDRAM ................................................................................. 17-92
Figure 17-68.
PCI Master Burst Write To SDRAM .................................................................................... 17-100
Figure 17-69. CPU Read From PCI Memory Slave, Nonprefetching ........................................................ 17-106
Figure 17-70.
CPU Read From PCI Memory Slave, Prefetching .............................................................. 17-108
Figure 17-71.
CPU Write To PCI Memory Slave ...................................................................................... 17-.112
Figure 17-72. PCI Memory To SDRAM DMA Transfer ............................................................................. 17-116
Figure 17-73. SDRAM To
PCI Memory DMA Transfer ............................................................................. 17-120
Figure 18-1. DMA
Controller External Bus Control Signals .......................................................................... 18-2
Figure 18-2. DMA
Polarity Configuration Register (DMAO_POL) ................................................................. 18-5
Figure 18-3. DMA
Sleep Mode Register (DMAO_SLP) ................................................................................. 18-7
Figure 18-4. DMA Status Register (DMAO_SR) ............................................................................................ 18-7
Figure 18-5. DMA
Channel Control Registers (DMAO_CRO-DMAO_CR3) ................................................... 18-8
Figure 18-6. DMA Source Address Registers (DMAO_SAQ-DMAO_SA3) .................................................. 18-11
Figure 18-7. DMA Destination Address Registers (DMAO_DAO-DMAO_DA3) ............................................
18-11
Figure 18-8. DMA Count Registers (DMAO_CTO-DMAO_CT3) ................................................................... 18-12
Figure 18-9. DMA Scatter/Gather Descriptor Address Registers (DMAO_SGO-DMAO_SG3) .................... 18-12
Figure 18-10. DMA Scatter/Gather Command Register (DMAO_SGC) ...................................................... 18-13
Figure 18-11.
Peripheral-to-Memory DMA Transfer ................................................................................... 18-18
Figure 18-12. Memory to
Peripheral DMA Transfer .................................................................................... 18-19
Figure 19-1. EMAC
in a Typical Ethernet Application ................................................................................... 19-2
Figure 19-2.
Internal EMAC Structure ........................................................................................................... 19-3
Figure 19-3. EMAC Loop-Back Modes ......................................................................................................... 19-5
Figure 19-4. MAL TX Descriptor
Control/Status Field ................................................................................... 19-7
Figure 19-5. Transmit
Packet Structure (Excluding VLAN Tagged and Control Packets) .......................... 19-10
Figure 19-6. MAL
RX Descriptor Control/Status Field ................................................................................ 19-12
Figure 19-7. Wake-Up
Packet Format ........................................................................................................ 19-14
Figure 19-8.
Control Packet Format ............................................................................................................ 19-16
Figure 19-9.
Integrated Flow Control Mechanism ....................................................................................... 19-17
Figure 19-10.
Pause Operation State Machine ........................................................................................... 19-18
Figure 19-11. Tagged MAC
Packet Format ................................................................................................ 19-19
Figure 19-12. Tag
Control Information Field Structure ............................................................................... 19-19
Figure 19-13. Receive Address Recognition
Flowchart .............................................................................. 19-22
Figure 19-14. Ethernet Address Filter Operation ........................................................................................ 19-23
Figure 19-15. Mode Register
° (EMACO_MRO) .......................................................................................... 19-25
Figure 19-16. Mode Register 1 (EMACO_MR1) .......................................................................................... 19-26
Figure 19-17. Transmit Mode Register
° (EMACO_TMRO) ......................................................................... 19-27
Figure 19-18. Transmit Mode Register 1 (EMACO_TMR1) ......................................................................... 19-28
Preliminary
Figures
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