IBM PowerPC 405GP

Figure 21-4. UART Interrupt Identification Registers (UARTx_IIR) .............................................................. 21-7
Figure 21-5. UART
FIFO Control Registers (UARTx_FCR) .............................................................. ; .......... 21-8
Figure 21-6. UART Line
Control Registers (UARTx_LCR) .............................................................. : ............ 21-9
Figure 21-7. UART Modem
Control Registers (UARTx_MCR) ................................................................... 21-10
Figure 21-8. UART Line Status Registers (UARTx_LSR) ........................................................................... 21-11
Figure 21-9. UART Modem Status Registers (UARTx_MSR) .................................................................... 21-13
Figure
21-10. Scratchpad Registers (UARTx_SCR) ................................................................................... 21-14
Figure 21-11. UART Baud-Rate Divisor Latch
(MSB) Registers (UARTx_DLM) ........................................ 21-14
Figure 21-12. UART Baud-Rate Divisor Latch
(LSB) Registers (UARTx_DLL) .......................................... 21-14
Figure 21-13. Chip
Control Register 0 (CPCO_CRO) .................................................................................. 21-17
Figure 22-1. 7-Bit Addressing ....................................................................................................................... 22-2
Figure 22-2. 1
O-Bit Addressing ..................................................................................................................... 22-2
Figure 22-3.
IICO Master Data Buffer (IICO_MDBUF) ................................................................................... 22-3
Figure 22-4.
FIFO Stages ........................................................ : .................................................................... 22-4
Figure 22-5.
IICO Slave Data Buffer (IICO_SDBUF) ...................................................................................... 22-5
Figure 22-6.
IICO Low Master Address Register (IICO_LMADR) .................................................................. 22-5
Figure 22-7.
IICO High Master Address Register (IICO_HMADR) ................................................................. 22-6
Figure 22-8.
IICO Control Register (IICO_CNTL) ........................................................................................... 22-7
Figure 22-9.
IICO Mode Control Register (IICO_MDCNTL) ........................................................................... 22-9
Figure
22-10. IICO Status Register (IICO_STS) .......................................................................................... 22-1 0
Figure 22-11. IICO Extended Status Register (IICO_EXTSTS) ................................................................... 22-12
Figure 22-12.
IICO Low Slave Address Register (IICO_LSADR) ................................................................. 22-14
Figure 22-13.
IICO High Slave Address Register (IICO_HSADR) ....................................... , ....................... 22-15
Figure 22-14.
IICO Clock Divide Register (IICO_CLKDIV) ........................................................................... 22-15
Figure 22-15.
IICO Interrupt Mask Register (IICO_INTRMSK) .................................................................... 22-16
Figure 22-16.
IICO Transfer Count Register (IICO_XFRCNT) ..................................................................... 22-17
Figure 22-17.
IICO Extended Control and Slave Status Register (IICO_XTCNTLSS) ................................. 22-18
Figure 22-18.
IICO Direct Control Register (IICO_DIRECTCNTL) ............................................................... 22-21
Figure 23-1.
GPIO Functional Block Diagram ............................................................................................... 23-2
Figure 23-2.
CPCO_CRO Bits Controlling GPIO ................................................ ; .......................................... 23-3
Figure 23-3.
GPIO Registers """.""""""""."" ... """""""".""."."" .. "" .. "".".""".""."" ............................ 23-5
Figure 25-1. Core Configuration Register
0 (CCRO) ................................................................................... 25-15
Figure 25-2. Chip
Control Register 0 (CPCO_CRO) .................................................................................... 25-17
Figure 25-3. Chip
Control Register 1 (CPCO_CR1) .................................................................................... 25-20
Figure 25-4. CPM Enable Register (CPCO_ER) ......................................................................................... 25-21
Figure 25-5.
CPM Force Register (CPCO_FR) ........................................................................................... 25-22
Figure 25-6. JTAG
10 Register (CPCO_JTAGID) ........................................................................................ 25-23
Figure 25-7.
PLL Mode Register (CPCO_PLLMR) ...................................................................................... 25-24
Figure 25-8. Chip
Pin Strapping Register (CPCO_PSR) ............................................................................. 25-26
Figure 25-9.
CPM Status Register (CPCO_SR) .......................................................................................... 25-28
Figure
25-10. Condition Register (CR) ....................................................................................................... 25-29
Figure 25-11. Count Register (CTR) ...........................................................................................................
25-30
Figure 25-12. Data Address Compare Registers (DAC1-DAC2) ............................................................... 25-31
Figure 25-13. Debug
Control Register 0 (DBCRO) ..................................................................................... 25-32
Figure 25-14. Debug
Control Register 1 (DBCR1) ..................................................................................... 25-34
Figure 25-15. Debug Status Register (DBSR) ................................................
" .......................................... 25-36
Preliminary Figures
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