IBM PowerPC 405GP User Manual

BA
PF
1
31
*
12111
*
t i
LT MSI
Figure 17-36. PCI PTM 2 BAR Register (PCICO_PTM2BAR)
31:12 BA
Base Address
Only corresponding bits in
These bits determine where in PCI PCILO_PTM2MS that are set to 1 are
Memory address space this region is writable. Bits
in PCILO_PTM2MS that
located.
are set to
0 cause the corresponding
Base Address register bits to be
always
O. PCILO_PTM2MS must be initialized
by a PLB master before any PCI device
can configure this register.
11 :4
BAZ
Base Address Always Zero
BAZ =
OxOO because the minimum size
of this range is 4KB.
3
PF
Prefetchable
PF = 1 to indicate that prefetching is
allowed.
2:1 LT
Location Type
LT = ObOO to indicate that the memory
space can be located anywhere
in the
32-bit address space.
0 MSI
Memory Space Indicator MSI = 0 to indicate memory space,
rather than
1/0 space.
17.5.3.16 PCI Subsystem Vendor 10 Register (PCICO_SBSYSVID)
PCICO_SBSYSVIO holds the vendor 10 for a subsystem or add-in board.
1
15
01
Figure 17-37. PCI Subsystem Vendor 10 Register (PCICO_SBSYSVIO)
1
15
:
0
PCI Subsystem Vendor ID
17.5.3.17 PCI Subsystem 10 Register (PCICO_SBSYSID)
PCICO_SBSYSIO holds the device 10 of a subsystem or add-in board.
Preliminary PCI Interface 17-39

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English