xx
CEIL(x)
EXTS(x)
PC
RESERVE
CIA
NIA
MS(addr, n)
EA
EAb
EA
b
:
b
ROTL((RS),n)
MASK(MB,ME)
instruction(EA)
Bit positions which are don't-cares.
Least
integer;:::
x.
The result of extending x on the left with sign bits.
Program counter.
Reserve bit; indicates whether a process has reserved a
block of
storage.
Current instruction address; the 32-bit address of the instruction being
described by a sequence of pseudocode. This address is used to set the
next instruction address
(NIA). Does not correspond to any architected
register.
Next instruction address; the 32-bit address of the next instruction to be
executed.
In
pseudocode, a successful branch is indicated by assigning
a
value to NIA. For instructions that do not branch, the NIA is CIA +4.
The number of bytes represented by
n at the location in main storage
represented by
addr.
Effective address; the 32-bit address, derived by applying indexing or
indirect addressing
rules to the specified operand, that specifies a
location in main storage.
A bit
in
an effective address.
A range of bits
in
an effective address.
Rotate
left; the contents of RS are shifted left the number of bits
specified by
n.
Mask having 1 s
in
positions MB through ME (wrapping if MB > ME) and
Os
elsewhere ..
An instruction operating on a data or instruction cache block associated
with an EA.
PPC405GP User's Manual
Preliminary
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