automatically generates Mil management packets, which conform to Clause 22
in
IEEE Std. 802.3u.
EMAC uses the EMACO_STACR for generation of the management packet.
EMAC
r
-----------------,
EMC_MDC
EMCMDClk
I
PHY_MDIO
1
PHY
t:>
..
I
EMCMDIO
Device
MAC
~
EMC_MDIO
<1
1
1
EMC_MDIO_EN
t
1
L
_________________
~
Figure 19-37. Management Interface with
PHY
19.8.2 EMAC - Mil Interface
See PPC405GP Data Sheet for information.
19.9 MAL - EMAC Packet Transfer Flow
The packet transfer flow consists of three phases. These three phases are used to define the details
of the EMAC-MAL protocol.
1. Packet phase - EMAC initiates a packet transfer operation. The packet transfer is started by a
command write. During command write MAL provides
control information for EMAC on a per-
packet basis. Following the command write, MAL begins the data transfer, during which MAL
transfers data between the buffers
located
in
the system's memory and EMAC. In transmit, the data
is transferred from the system's memory to EMAC, while
in
receive, the data is transferred from
EMAC to the system's memory buffers.
- EMAC remains
in
the packet phase until the data transfer has been completed
or
a ready status
can be returned to MAL. The packet phase ends when EMAC deasserts the FRAME
signal
associated with the related channel (receive/transmit).
- The packet phase is defined by activity of an appropriate FRAME
signal.
2. Status phase - This is the second phase of the packet transfer. Following the de-assertion of the
FRAME
signal, EMAC switches to the status phase. At this stage, EMAC uses an appropriate
signal as a request for service which is interpreted by MAL as a request for status read.
3~
Idle phase - EMAC moves into the idle phase following a reset
or
after status was transferred (end
of status phase). During the
idle phase, EMAC cannot send any signals to MAL, nor can MAL send
any active
signals to EMAC. EMAC exits the idle phase by asserting the FRAME signal (and
entering the packet phase described above).
Idle phase can be skipped when EMAC operates
in
multiple transfer mode.
Preliminary
Ethernet Media Access Controller
19-43
To Next Page
Loading...
