The error status field includes an "Error Valid" bit which indicates whether there is valid error
information
in
the error status field
or
not. The error status field is not valid when the "Error Valid" bit
is
cleared (by writing 1 to this bit).
Interrupt status - Every error detected by MAL sets a related bit
in
the interrupt status field.
Software
can clear an interrupt status bit by writing 1 to the bit to be cleared. The bits
in
this field
are accumulative which allows more than one interrupt to be indicated
in
the register.
Error Status Bits
Interrupt Status Bits
,-----------~/'~------------~
,-------------~/
Non-accumu¥tive field
Accumul~e
field
Valid
bit for
Error
Status bits
Overwritten
in
non-locked mode
Locked
in
locked mode
Figure 20-9. Error Status Register Field
20.7.3.4 Operational Error Modes
MAL can operate
in
two different error handling modes:
• Locked Error Mode: Information about the error is written to the Error Status Register, and the Valid
bit
in
that register is set. Information
in
the Error Status field of the register stays locked until
software unlocks it by resetting the error Valid bit. The Interrupt Status bits of the Error Status
Register are not locked
in
this mode, so software can find out if more errors occur. However, the
Error
Status field applies only to the first error that is locked.
•
Non-Locked Error Mode: Information about the error is written in the Error Status Register, and the
error
Valid bit is set. Each new error will be overwritten, so the information in the Error Status Field
is valid only for the last error that occurred.
In
both modes, each error written
in
the error description field will set the error Valid bit, and it is the
responsibility of software to reset this bit.
The error
handling mode is programmed
in
the MAL Configuration Register (see "MAL Configuration
Register
(MALO_CFG)" on page 20-25).
20.7.3.5 Resolution
of
an
Error Situation
When MAL encounters an error, it reacts as follows:
•
Writes information about the error
in
the Error Status Register (ESR). This information includes the
channel ID of the channel which caused the error (if known), the bus on which the error occurred,
and the kind of error that occurred.
• Resets the channel that caused the error (if known) in the Channel Active Register.
• Updates the Interrupt Status bits
in
the MALO_ESA. Then, depending on the mask defined
in
MALO_IER (Interrupt Enable Register), it may send an interrupt to software
(in
PPC405GP, it
sends it to the
Universal Interrupt Controller).
Preliminary
Memory Access Layer
20-21
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