1
0
11
31
1
Figure
20-17. RX End
of
Buffer
Interrupt
Status
Register
(MALO_RXEOBISR)
0
Receive Channel End-ot-Bufter Interrupt Each bit represents its related
channel (bit
0 for channel
0,
etc.).
Writing 1 to a bit resets it.
There is only one RX channel
in
the
PPC40SGP.
1
:31
Reserved
20.9 Error Registers
The following paragraphs describe MAL error registers. For more information about MAL errors see
"Error
Handling" on page 20-19.
20.9.1
MAL Error Status Register (MALO_ESR)
This register holds the information about the error that occurred and the interrupts status. The register
includes the
following fields:
•
Error
status
bits
- This field holds the error information. The information includes the number of
the channel on which the error occurred (if known) and the type of the error. The error can be either
the last detected error or a locked error if "Locked error
mode" is active. (See "Operational Error
Modes" on page
20-21 for description of the Locked error mode.)
The error status field includes an "Error
Valid" bit which indicates whether there
is
an error information
in the error status field or not. The error status bits are not
valid when the "Error Valid" bit is cleared
(by writing 1 to this bit).
•
Interrupt
status
bits
- Every error detected by MAL sets a related bit
in
the interrupt status field.
The interrupt status bits may
be
cleared by software by writing 1 to the bit to
be
cleared. The bits
in
this field are accumulative (more than one interrupt may be indicated here). These bits are masked
by the
IER (Interrupt Enable Register) to create a maskable interrupt, which
is
implemented by the
MAL_SERR_INT signal (connected to the UIC on the PPC405GP).
Note:
In
order to reset the interrupt bits and the Error valid bit
in
the Error Status register, 1 must be
written to the related bit. Writing
0 has no effect.
More than one bit can
be
cleared at a time and only RIW bits can be reset.
Preliminary Memory Access Layer 20-29
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