Sharp LH79524 - Page 11

LH79524/LH79252 User’s Guide Table of Contents
Version 1.0 ix
10.1.7.1 SSP Protocol Error Interrupt.........................................................10-11
10.1.7.2 External Codec Protocol Error Interrupt .......................................10-11
10.1.7.3 Transmit FIFO Underrun Interrupt................................................10-11
10.1.7.4 Receive Interrupt..........................................................................10-12
10.1.7.5 Transmit Interrupt.........................................................................10-12
10.1.7.6 Receive Overrun Interrupt ............................................................10-12
10.1.7.7 Receive Timeout Interrupt ............................................................10-12
10.1.7.8 I
2
SINTR ........................................................................................10-12
10.2 Register Reference ....................................................................................10-13
10.2.1 Memory Map .......................................................................................10-13
10.2.2 Register Descriptions ..........................................................................10-14
10.2.2.1 Control Register (CTRL)...............................................................10-14
10.2.2.2 Status Register (STAT) ................................................................10-16
10.2.2.3 Interrupt Mask Set or Clear Register (IMSC)................................10-17
10.2.2.4 Raw Interrupt Status Register (RIS).............................................10-18
10.2.2.5 Masked Interrupt Status Register (MIS).......................................10-19
10.2.2.6 Interrupt Clear Register (ICR).......................................................10-20
Chapter 11 – I/O Configuration
11.1 Theory of Operation .....................................................................................11-1
11.2 Register Reference ......................................................................................11-2
11.2.1 Memory Map .........................................................................................11-2
11.2.2 Register Definitions ...............................................................................11-4
11.2.2.1 Multiplexing Control 1 Register (MUXCTL1) ..................................11-4
11.2.2.2 Resistor Configuration Control 1 Register (RESCTL1) ..................11-5
11.2.2.3 Multiplexing Control 3 Register (MUXCTL3) ..................................11-6
11.2.2.4 Resistor Configuration Control 3 Register (RESCTL3) ..................11-6
11.2.2.5 Multiplexing Control 4 Register (MUXCTL4) ..................................11-7
11.2.2.6 Resistor Configuration Control 4 Register (RESCTL4) ..................11-8
11.2.2.7 Multiplexing Control 5 Register (MUXCTL5) ..................................11-9
11.2.2.8 Resistor Configuration Control 5 Register (RESCTL5) ................11-10
11.2.2.9 Multiplexing Control 6 Register (MUXCTL6) ................................11-12
11.2.2.10 Resistor Configuration Control 6 Register (RESCTL6) ..............11-13
11.2.2.11 Multiplexing Control 7 Register (MUXCTL7) ..............................11-14
11.2.2.12 Resistor Configuration Control 7 Register (RESCTL7) ..............11-16
11.2.2.13 Multiplexing Control 10 Register (MUXCTL10) ..........................11-18
11.2.2.14 Resistor Configuration Control 10 Register (RESCTL10) ..........11-20
11.2.2.15 Multiplexing Control 11 Register (MUXCTL11) ..........................11-22
11.2.2.16 Resistor Configuration Control 11 Register (RESCTL11) ..........11-24
11.2.2.17 Multiplexing Control 12 Register (MUXCTL12) ..........................11-26
11.2.2.18 Resistor Configuration Control 12 Register (RESCTL12) ..........11-27
11.2.2.19 Resistor Configuration Control 13 Register (RESCTL13) ..........11-29
11.2.2.20 Multiplexing Control 14 Register (MUXCTL14) ..........................11-30
11.2.2.21 Multiplexing Control 15 Register (MUXCTL15) ..........................11-32
11.2.2.22 Resistor Configuration Control 15 Register (RESCTL15) ..........11-32
11.2.2.23 Resistor Configuration Control 17 Register (RESCTL17) ..........11-33
11.2.2.24 Multiplexing Control 19 Register (MUXCTL19) ..........................11-34
11.2.2.25 Resistor Configuration Control 19 Register (RESCTL19) ..........11-36