Sharp LH79524 - Page 10

Table of Contents LH79524/LH79252 User’s Guide
viii Version 1.0
7.5.2.24 Static Memory Read Delay Registers (SWAITRDx).......................7-56
7.5.2.25 Static Memory Page Mode Read Delay Registers
(SWAITPAGEx)........................................................................................7-57
7.5.2.26 Static Memory Write Delay Registers (SWAITWRx) ......................7-58
7.5.2.27 Static Memory Turn Around Delay Registers (STURNx)................7-59
Chapter 8 – General Purpose Input/Output
8.1 Theory of Operation .........................................................................................8-1
8.1.1 Port Configuration .....................................................................................8-1
8.1.1.1 Multiplexing.........................................................................................8-2
8.2 Register Reference ..........................................................................................8-7
8.2.1 Memory Map .............................................................................................8-7
8.2.2 Register Descriptions ................................................................................8-8
8.2.2.1 Port A/C/E/G/I/K/M Data Registers (P1DRx)......................................8-8
8.2.2.2 Port B/D/F/H/J/L/N Data Register (P2DRx)........................................8-9
8.2.2.3 Port A/C/E/G/I/K Data Direction Register (P1DDRx)........................8-10
8.2.2.4 Port B/D/F/H/L/N Data Direction Register ........................................8-11
Chapter 9 – I
2
C Module
9.1 Theory of Operation .........................................................................................9-2
9.1.1 Setting I
2
C Clock Timing ...........................................................................9-3
9.1.2 Interrupt Handling......................................................................................9-4
9.1.3 Slave Mode ...............................................................................................9-5
9.1.4 Master Mode .............................................................................................9-5
9.1.5 Resetting a Locked Slave..........................................................................9-5
9.2 Register Reference ..........................................................................................9-6
9.2.1 Memory Map .............................................................................................9-6
9.2.2 Register Definitions ...................................................................................9-7
9.2.2.1 I
2
C Configuration Register (ICCON)...................................................9-7
9.2.2.2 I
2
C Slave Address Register (ICSAR) .................................................9-8
9.2.2.3 I
2
C Upper Slave Address Register (ICUSAR)....................................9-9
9.2.2.4 I
2
C Data Register (ICDATA)...............................................................9-9
9.2.2.5 I
2
C Clock High Time Register (ICHCNT)..........................................9-10
9.2.2.6 I
2
C Clock Low Time Register (ICLCNT)...........................................9-10
9.2.2.7 I
2
C Status Register (ICSTAT)...........................................................9-11
Chapter 10 – I
2
S Converter
10.1 Theory of Operation .....................................................................................10-3
10.1.1 Conversion ............................................................................................10-3
10.1.2 Driving/Latching Edges .........................................................................10-4
10.1.3 Transmission.........................................................................................10-5
10.1.3.1 Master Mode Transmission ............................................................10-5
10.1.3.2 Slave Mode Transmission..............................................................10-6
10.1.4 Reception ..............................................................................................10-7
10.1.4.1 Master Mode Reception .................................................................10-7
10.1.4.2 Slave Mode Reception ...................................................................10-9
10.1.5 Suppression of SSPFSSIN..................................................................10-10
10.1.6 Channel Management.........................................................................10-10
10.1.7 Interrupts .............................................................................................10-11