LH79524/LH79252 User’s Guide Table of Contents
Version 1.0 vii
7.2.4.6 Extended Wait Transfers..................................................................7-17
7.3 Interfacing with NAND Flash ..........................................................................7-17
7.3.1 Booting Example .....................................................................................7-17
7.3.2 General NAND Flash Access..................................................................7-20
7.3.2.1 Transaction Example........................................................................7-20
7.3.2.2 16-bit Example Transaction..............................................................7-21
7.3.2.3 Address Examples............................................................................7-21
7.4 Dynamic Memory ...........................................................................................7-22
7.4.1 Write-protection.......................................................................................7-22
7.4.2 Access Sequencing and Memory Width..................................................7-22
7.4.3 Bus Address Mapping .............................................................................7-22
7.4.4 Data Mask Signals ..................................................................................7-27
7.5 Register Reference ........................................................................................7-28
7.5.1 Memory Map ...........................................................................................7-28
7.5.2 Register Definitions .................................................................................7-30
7.5.2.1 Control Register (CONTROL)...........................................................7-30
7.5.2.2 Status Register (STATUS) ...............................................................7-31
7.5.2.3 Configuration Register (CONFIG) ....................................................7-32
7.5.2.4 Dynamic Memory Control Register (DYNMCTRL) ...........................7-33
7.5.2.5 Dynamic Refresh Register (DYNMREF) ..........................................7-34
7.5.2.6 Dynamic Memory Read Configuration Register (DYNMRCON).......7-35
7.5.2.7 Dynamic Precharge Command Period Register (PRECHARGE) ....7-36
7.5.2.8 Dynamic Memory Active to Precharge Command Period
Register (DYNM2PRE).............................................................................7-37
7.5.2.9 Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)........7-38
7.5.2.10 Dynamic Memory Last Data Out to Active Time
Register (DOACTIVE) ..............................................................................7-39
7.5.2.11 Dynamic Memory Data-In to Active Time Register (DIACTIVE).....7-40
7.5.2.12 Dynamic Memory Write Recovery Time Register (DWRT) ............7-41
7.5.2.13 Dynamic Memory Active to Active Command
Period Register (DYNACTCMD) ..............................................................7-42
7.5.2.14 Dynamic Memory Auto-Refresh Period, and Auto-Refresh
to Active Command Period Register (DYNAUTO) ...................................7-43
7.5.2.15 Dynamic Memory Exit Self-Refresh to Active Command
Time Register (DYNREFEXIT).................................................................7-44
7.5.2.16 Dynamic Memory Active Bank A to Active Bank B
Time Register (DYNACTIVEAB) ..............................................................7-45
7.5.2.17 Dynamic Memory Load Mode Register to
Active Command Time Register (DYNAMICTMRD) ................................7-46
7.5.2.18 Static Memory Extended Wait Register (WAIT) .............................7-47
7.5.2.19 Dynamic Configuration Register for nDCS0
and nDCS1 (DYNCFGx)...........................................................................7-48
7.5.2.20 Dynamic Memory RAS and CAS Delay Register for
nDCS0 and nDCS1 (DYNRASCASx).......................................................7-51
7.5.2.21 Static Memory Configuration Register (SCONFIGx) ......................7-52
7.5.2.22 Static Memory Write Enable Delay Registers (SWAITWENx)........7-54
7.5.2.23 Static Memory Output Enable Delay Registers (SWAITOENx)......7-55
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