Sharp LH79524 - Page 8

Table of Contents LH79524/LH79252 User’s Guide
vi Version 1.0
6.3.3.3 Single Collision Frames (SINGLECOL)............................................6-38
6.3.3.4 Multiple Collision Frames (MULTFRM) ............................................6-39
6.3.3.5 Frames Received OK (FRMRXOK)..................................................6-39
6.3.3.6 Frame Check Sequence Errors (FRCHK) ........................................6-40
6.3.3.7 Alignment Errors (ALIGNERR).........................................................6-40
6.3.3.8 Deferred Transmission Frames (DEFTXFRM).................................6-41
6.3.3.9 Late Collisions (LATECOL) ..............................................................6-41
6.3.3.10 Excessive Collisions (EXCOL) .......................................................6-42
6.3.3.11 Transmit Underrun Errors (TXUNDER)..........................................6-42
6.3.3.12 Carrier Sense Errors (SENSERR)..................................................6-43
6.3.3.13 Receive Resource Errors (RXRERR).............................................6-44
6.3.3.14 Receive Overrun Errors (RXOVERR).............................................6-44
6.3.3.15 Receive Symbol Errors (RXSYMERR)...........................................6-45
6.3.3.16 Excessive Length Error Register (LENERR)..................................6-45
6.3.3.17 Receive Jabbers (RXJAB)..............................................................6-46
6.3.3.18 Undersize Frames (UNDERFRM) ..................................................6-46
6.3.3.19 SQE Test Errors (SQERR).............................................................6-47
6.3.3.20 Received Length Field Mismatch (RXLEN)....................................6-47
6.3.3.21 Transmitted Pause Frames (TXPAUSEFM)...................................6-48
6.3.4 Matching Registers..................................................................................6-49
6.3.4.1 Hash Register Bottom (HASHBOT)..................................................6-49
6.3.4.2 Hash Register Top (HASHTOP).......................................................6-49
6.3.4.3 Specific Address 1 Bottom (SPECAD1BOT)....................................6-50
6.3.4.4 Specific Address 1 Top (SPECAD1TOP).........................................6-50
6.3.4.5 Specific Address 2 Bottom (SPECAD2BOT)....................................6-51
6.3.4.6 Specific Address 2 Top (SPECAD2TOP).........................................6-51
6.3.4.7 Specific Address 3 Bottom (SPECAD3BOT)....................................6-52
6.3.4.8 Specific Address 3 Top (SPECAD3TOP).........................................6-52
6.3.4.9 Specific Address 4 Bottom (SPECAD4BOT)....................................6-53
6.3.4.10 Specific Address 4 Top (SPECAD4TOP).......................................6-53
6.3.4.11 Type ID Checking (IDCHK) ............................................................6-54
Chapter 7 – External Memory Controller
7.1 Theory of Operation .........................................................................................7-1
7.1.1 External Memory Map ...............................................................................7-3
7.1.1.1 nCS1 Memory Configuration..............................................................7-3
7.2 Static Memory ..................................................................................................7-3
7.2.1 Static Memory Operation...........................................................................7-3
7.2.2 Hardware Design.......................................................................................7-5
7.2.2.1 Address Connectivity..........................................................................7-5
7.2.3 Software Design........................................................................................7-9
7.2.3.1 Simple Shifting Subroutine .................................................................7-9
7.2.4 Static Memory Device Selection..............................................................7-10
7.2.4.1 Static Memory Timing Control ..........................................................7-10
7.2.4.2 Bus Turnaround................................................................................7-16
7.2.4.3 Byte Lane Control.............................................................................7-16
7.2.4.4 Write Protection................................................................................7-16
7.2.4.5 nWAIT Transfers ..............................................................................7-16