Sharp LH79524 - Page 7

LH79524/LH79252 User’s Guide Table of Contents
Version 1.0 v
Chapter 6 – Ethernet MAC Controller
6.1 Theory of Operation .........................................................................................6-2
6.1.1 Operational Overview................................................................................6-3
6.1.1.1 Setup ..................................................................................................6-4
6.1.1.2 Statistics.............................................................................................6-4
6.1.1.3 Detailed Descriptions..........................................................................6-4
6.1.2 Memory Interface ......................................................................................6-4
6.1.2.1 FIFO ...................................................................................................6-4
6.1.2.2 Receive Buffers ..................................................................................6-4
6.1.2.3 Transmit Buffer...................................................................................6-7
6.1.3 Receive Block............................................................................................6-9
6.1.4 Transmit Block...........................................................................................6-9
6.1.4.1 Pause Frame Support ......................................................................6-10
6.1.5 Address Checking Block .........................................................................6-11
6.1.5.1 Broadcast Address ...........................................................................6-12
6.1.5.2 Hash Addressing ..............................................................................6-12
6.1.5.3 Copy All Frames (Promiscuous Mode).............................................6-12
6.1.5.4 Type ID Checking.............................................................................6-13
6.1.5.5 VLAN Support...................................................................................6-13
6.2 Programming Model.......................................................................................6-13
6.2.1 Initialization..............................................................................................6-14
6.2.1.1 Receive Buffer List ...........................................................................6-14
6.2.1.2 Transmit Buffer List ..........................................................................6-16
6.2.1.3 Transmitting Frames.........................................................................6-16
6.2.1.4 Local Loop Back Mode.....................................................................6-16
6.2.1.5 PHY Maintenance.............................................................................6-17
6.2.1.6 Interrupts ..........................................................................................6-17
6.3 Register Reference ........................................................................................6-18
6.3.1 Memory Map ...........................................................................................6-18
6.3.2 Control, Configuration, And Status Register Definitions..........................6-20
6.3.2.1 Network Control Register (NETCTL)................................................6-20
6.3.2.2 Network Configuration Register (NETCONFIG)...............................6-22
6.3.2.3 Network Status Register (NETSTATUS)..........................................6-24
6.3.2.4 Transmit Status Register (TXSTATUS)............................................6-25
6.3.2.5 Receive Buffer Queue Pointer (RXBQP)..........................................6-27
6.3.2.6 Transmit Buffer Queue Pointer (TXBQP).........................................6-28
6.3.2.7 Receive Status Register (RXSTATUS) ............................................6-29
6.3.2.8 Interrupt Status Register (INSTATUS) .............................................6-30
6.3.2.9 Interrupt Enable Register (ENABLE)................................................6-32
6.3.2.10 Interrupt Disable Register (DISABLE)............................................6-33
6.3.2.11 Interrupt Mask Register (MASK).....................................................6-34
6.3.2.12 PHY Maintenance Register (PHYMAINT) ......................................6-35
6.3.2.13 Pause Time Register (PAUSETIME)..............................................6-36
6.3.2.14 Transmit Pause Quantum (TXPAUSEQUAN)................................6-36
6.3.3 Statistics Register Definitions..................................................................6-37
6.3.3.1 Pause Frames Received (PAUSEFRRX).........................................6-37
6.3.3.2 Frames Transmitted OK (FRMTXOK) ..............................................6-38