Sharp LH79524 - Page 16

Table of Contents LH79524/LH79252 User’s Guide
xiv Version 1.0
17.2.3.6 OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP)...17-26
17.2.3.7 Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1)..17-27
17.2.3.8 Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2) ...17-29
17.2.3.9 Count 0 Register (OUTCOUNT0).................................................17-30
17.2.3.10 Count 1 Register (OUTCOUNT1)...............................................17-30
17.2.3.11 Out Count 2 Register (OUTCOUNT2)........................................17-31
17.2.3.12 FIFOs for Endpoints 0-3 (FIFOx)................................................17-31
17.2.3.13 Pending DMA Interrupts Register (INTR)...................................17-32
17.2.3.14 DMA Channel x Control Register (CNTLx).................................17-33
17.2.3.15 DMA Channel x AHB Memory Address Register .......................17-34
17.2.3.16 DMA Channel x Byte Count Register (COUNTx) .......................17-34
Chapter 18 – Vectored Interrupt Controller
18.1 Theory of Operation .....................................................................................18-1
18.1.1 VIC Interrupt Listing...............................................................................18-2
18.1.2 Vectored Interrupts................................................................................18-3
18.1.3 External Interrupts.................................................................................18-3
18.1.4 Clearing Interrupts.................................................................................18-4
18.1.5 Priority ...................................................................................................18-4
18.1.6 External Level-Sensitive Interrupts........................................................18-4
18.1.7 Software Guidelines ..............................................................................18-4
18.2 Register Reference ......................................................................................18-5
18.2.1 Memory Map .........................................................................................18-5
18.2.2 Register Descriptions ............................................................................18-6
18.2.2.1 IRQ Status Register (IRQSTATUS)................................................18-6
18.2.2.2 FIQ Status Register (FIQSTATUS) ................................................18-7
18.2.2.3 Raw Interrupt Status Register (RAWINTR) ....................................18-7
18.2.2.4 Interrupt Select Register (INTSELECT)..........................................18-8
18.2.2.5 Interrupt Enable Register (INTENABLE) ........................................18-8
18.2.2.6 Interrupt Enable Clear Register (INTENCLEAR)............................18-9
18.2.2.7 Software Interrupt Register (SOFTINT)........................................18-10
18.2.2.8 Software Interrupt Clear Register (SOFTINTCLEAR) ..................18-11
18.2.2.9 Vector Address Register (VECTADDR) .......................................18-12
18.2.2.10 Default Vector Address Register (DEFVECTADDR)..................18-12
18.2.2.11 Vector Address Registers (VECTADDRx)..................................18-13
18.2.2.12 Vector Control Registers (VECTCTRLx) ....................................18-14
18.2.2.13 Interrupt Test Output Register (ITOP)........................................18-15
Chapter 19 – Watchdog Timer
19.1 Theory of Operation .....................................................................................19-1
19.1.1 WDT Operation Details .........................................................................19-3
19.2 Register Reference ......................................................................................19-4
19.2.1 Memory Map .........................................................................................19-4
19.2.2 Register Descriptions ............................................................................19-5
19.2.2.1 Control Register (CTL) ...................................................................19-5
19.2.2.2 Counter Reset Register (RST) .......................................................19-6
19.2.2.3 Status Register (STATUS) .............................................................19-7
19.2.2.4 Current Watchdog Count Registers (COUNT[3:0]) ........................19-8
Chapter 20 – Glossary