Sharp LH79524 - Page 18

List of Figures LH79524/LH79252 User’s Guide
xvi Version 1.0
Chapter 7 – External Memory Controller
Figure 7-1. External Memory Controller Block Diagram.............................................7-2
Figure 7-2. Automatic Address Shifting......................................................................7-4
Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices .............................7-6
Figure 7-4. 16-bit Memory Bank Constructed From 8-bit Devices .............................7-6
Figure 7-5. 8-bit Memory Bank...................................................................................7-6
Figure 7-6. 32-bit (left) and 16-bit (right) Memory Banks Constructed
From 16-bit Devices ...............................................................................................7-7
Figure 7-7. 32-bit Memory Bank Constructed From a Single 32-bit Device...............7-7
Figure 7-8. Typical Memory Connection Diagram......................................................7-8
Figure 7-9. Pre-shifting Routine .................................................................................7-9
Figure 7-10. Static Read Transaction with Zero Wait States ...................................7-11
Figure 7-11. Static Read Transaction with Three Wait States .................................7-12
Figure 7-12. Static Write Transaction with Zero Wait States....................................7-13
Figure 7-13. Static Write Transaction with Two Wait States ....................................7-15
Figure 7-14. Connection to NAND Flash..................................................................7-19
Figure 7-15. NAND Flash Timing Example..............................................................7-21
Chapter 9 – I
2
C Module
Figure 9-1. I
2
C Module Block Diagram.......................................................................9-1
Figure 9-2. I
2
C Bus Protocol ......................................................................................9-2
Chapter 10 – I
2
S Converter
Figure 10-1. I
2
S Converter Block Diagram...............................................................10-2
Figure 10-2. TI SSP Frame Format..........................................................................10-3
Figure 10-3. I
2
S Format............................................................................................10-3
Figure 10-4. Driving/Latching Diagram.....................................................................10-4
Figure 10-5. I
2
S Master Mode Transmission Block Diagram ...................................10-5
Figure 10-6. I
2
S Master Mode Transmission Timing Diagram.................................10-5
Figure 10-7. I
2
S Slave Mode Transmission Block Diagram .....................................10-6
Figure 10-8. I
2
S Slave Mode Transmission Timing Diagram ...................................10-7
Figure 10-9. I
2
S Master Mode Reception Block Diagram ........................................10-8
Figure 10-10. I
2
S Master Mode Reception Timing Diagram ....................................10-8
Figure 10-11. I
2
S Slave Mode Reception Block Diagram ........................................10-9
Figure 10-12. I
2
S Slave Mode Reception Timing Diagram ......................................10-9
Chapter 12 – Real Time Clock
Figure 12-1. RTC Block Diagram .............................................................................12-1
Chapter 13 – Reset, Clock, and Power Controller
Figure 13-1. RCPC Block Diagram ..........................................................................13-2
Figure 13-2. USB Clock Divider Chain.....................................................................13-4
Figure 13-3. Remap = 0b00 ...................................................................................13-11
Figure 13-4. Remap = 0b01 ...................................................................................13-12
Figure 13-5. Remap = 0b10 ...................................................................................13-12
Figure 13-6. Remap = 0b11 ...................................................................................13-13