Sharp LH79524 - Page 4

Table of Contents LH79524/LH79252 User’s Guide
ii Version 1.0
1.4.2 Hardware Requirements at Reset...........................................................1-10
1.4.2.1 Floating Inputs..................................................................................1-10
1.4.2.2 Test Pins...........................................................................................1-10
1.4.2.3 Active Pull Ups .................................................................................1-11
1.5 AHB Bus Master Priority and Arbitration ........................................................1-12
1.6 Memory Interface Architecture .......................................................................1-12
1.7 Instruction and Data Cache............................................................................1-17
1.8 Memory Management Unit (MMU).................................................................1-17
Chapter 2 – Analog-to-Digital Converter/Brownout Detector
2.1 Theory of Operation .........................................................................................2-1
2.1.1 Operational Summary ...............................................................................2-1
2.1.2 Bias-and-Control Network .........................................................................2-3
2.1.3 Clock Generator ........................................................................................2-5
2.1.4 Brownout Detector.....................................................................................2-5
2.1.5 SAR Architecture.......................................................................................2-5
2.1.6 Battery Control Feature.............................................................................2-7
2.1.7 Timing Formulas........................................................................................2-8
2.1.8 Interrupts ...................................................................................................2-8
2.1.8.1 Brownout Interrupt..............................................................................2-8
2.1.8.2 Pen Interrupt.......................................................................................2-9
2.1.8.3 End-of-Sequence Interrupt.................................................................2-9
2.1.8.4 FIFO Watermark Interrupt ..................................................................2-9
2.1.8.5 FIFO Overrun Interrupt.......................................................................2-9
2.1.9 Application Details.....................................................................................2-9
2.2 Register Reference ........................................................................................2-10
2.2.1 Memory Map ...........................................................................................2-10
2.2.2 Register Descriptions ..............................................................................2-11
2.2.2.1 High Word Register (HW).................................................................2-11
2.2.2.2 Low Word Register (LW)..................................................................2-13
2.2.2.3 Results Register (RR).......................................................................2-14
2.2.2.4 Interrupt Mask Register (IM).............................................................2-15
2.2.2.5 Power Configuration Register (PC) ..................................................2-16
2.2.2.6 General Configuration Register (GC) ...............................................2-18
2.2.2.7 General Status Register (GS)...........................................................2-19
2.2.2.8 Interrupt Status Register (IS)............................................................2-20
2.2.2.9 FIFO Status Register (FS)................................................................2-21
2.2.2.10 Control Bank Registers...................................................................2-22
2.2.2.11 Idle High Word Register (IHWCTRL)..............................................2-23
2.2.2.12 Idle Low Word Register (ILWCTRL)...............................................2-24
2.2.2.13 Masked Interrupt Status Register (MIS).........................................2-25
2.2.2.14 Interrupt Clear Register (IC) ...........................................................2-26