Sharp LH79524 - Page 5

LH79524/LH79252 User’s Guide Table of Contents
Version 1.0 iii
Chapter 3 – Boot Controller
3.1 Theory of Operation .........................................................................................3-2
3.1.1 Boot Device Determination........................................................................3-2
3.1.1.1 NAND Flash Operation.......................................................................3-4
3.1.2 Hardware Design Considerations..............................................................3-4
3.1.2.1 Active Pullups To Signal Boot Mode ..................................................3-4
3.1.2.2 NAND Flash Hardware Design...........................................................3-5
3.1.3 Booting Using the I2C Interface ................................................................3-6
3.1.4 Booting from UART ...................................................................................3-7
3.2 Register Reference ..........................................................................................3-7
3.2.1 Memory Map .............................................................................................3-7
3.2.2 Register Definitions ...................................................................................3-8
3.2.2.1 Power-up Boot Configuration Register (PBC)....................................3-8
3.2.3 nCS1 Override Register (CS1OV).............................................................3-9
3.2.4 External Peripheral Mapping Register (EPM) .........................................3-10
Chapter 4 – Color Liquid Crystal Display Controller
4.1 Introduction.......................................................................................................4-1
4.1.1 LCD Panel Architecture.............................................................................4-2
4.2 CLCDC Features..............................................................................................4-3
4.3 Theory of Operation .........................................................................................4-3
4.3.1 Supported Displays and Panels ................................................................4-5
4.3.2 Frame Buffer .............................................................................................4-5
4.3.3 LCD DMA FIFOs .......................................................................................4-5
4.3.4 Pixel Serializer...........................................................................................4-6
4.3.5 How Pixels are Stored in Memory.............................................................4-6
4.3.6 Palette RAM ..............................................................................................4-8
4.3.6.1 Grayscale Algorithm ...........................................................................4-9
4.3.6.2 Interrupts ............................................................................................4-9
4.3.6.3 LCD Panel Resolutions ......................................................................4-9
4.3.7 LCD Data Multiplexing.............................................................................4-12
4.3.8 LCD Interface Timing Signals..................................................................4-13
4.3.8.1 LCD Horizontal Timing Signals.........................................................4-13
4.3.8.2 LCD Vertical Timing Signals.............................................................4-14
4.3.9 LCD Power Sequencing at Turn-On and Turn-Off ..................................4-15
4.3.9.1 Minimizing a Retained Image on the LCD........................................4-16
4.3.10 Interrupts ...............................................................................................4-16
4.4 Advanced LCD Interface ................................................................................4-17
4.4.1 ALI Theory of Operation..........................................................................4-18
4.4.2 ALI Operating Modes ..............................................................................4-18
4.4.2.1 Bypass Mode....................................................................................4-18
4.4.2.2 Active Mode......................................................................................4-18
4.5 CLCDC Register Reference...........................................................................4-19
4.5.1 Enabling the CLCDC...............................................................................4-19
4.5.2 CLCDC Memory Map..............................................................................4-19
4.5.3 CLCDC Register Descriptions.................................................................4-20
4.5.3.1 Horizontal Timing Panel Control Register (TIMING0) ......................4-20
4.5.3.2 Vertical Timing Panel Control Register (TIMING1)...........................4-22