PCI Command Register (PCICO_CMD) ............................................................................................. 17-31
PCI
Status Register (PCICO_STATUS) .............................................................................................. 17-33
PCI Revision
10
Register (PCICO_REVID) ......................................................................................... 17-34
PCI
Class Register (PCICO_CLS) ...................................................................................................... 17-35
PCI
Cache Line Size Register (PCICO_CACHELS) ........................................................................... 17-35
PCI Latency Timer Register (PCICO_LATTIM) .................................................................................. 17-36
PCI Header Type Register (PCICO_HDTYPE) ................................................................................... 17-36
PCI Built-In Self Test (BIST) Control Register (PCICO_BIST) ............................................................ 17-37
Unused
PCI Base Address Register Space ....................................................................................... 17-37
PCI
PTM 1 BAR (PCICO_PTM1BAR) .................................................................................. : ............. 17-37
PCI PTM 2 BAR (PCICO_PTM2BAR) ................................................................................................ 17-38
PCI Subsystem Vendor
10
Register (PCICO_SBSYSVID) ................................................................. 17-39
PCI Subsystem
10
Register (PCICO_SBSYSID) ................................................................................ 17-39
PCI Capabilities Pointer (PCICO_CAP) .............................................................................................. 17-40
PCllnterrupt
Line Register (PCICO_INTLN) ...................................................................................... 17-40
PCllnterrupt Pin Register (PCICO_INTPN) ........................................................................................ 17-41
PCI Minimum Grant Register (PCICO_MINGNT) ............................................................................... 17-41
PCI Maximum Latency Register (PCICO_MAXLTNCY) ..................................................................... 17-41
PCllnterrupt Control/Status Register (PCICO_ICS) ........................................................................... 17-42
Error
Enable Register (PCICO_ERREN) ............................................................................................ 17-42
Error Status Register
(PCICO_ERRSTS) ........................................................................................... 17-43
Bridge
Options 1 Register (PCICO_BRDGOPT1) .............................................................................. 17-44
PLB Slave Error Syndrome Register ° (PCICO_PLBBESRO) ............................................................ 17-45
PLB Slave Error Syndrome Register 1 (PCICO_PLBBESR1) ............................................................ 17-47
PLB Slave Error Address Register (PCICO_PLBBEAR) .................................................................... 17-48
Capability
Identifier (PCICO_CAPID) .................................................................................................. 17-49
Next
Item Pointer (PCICO_NEXTIPTR) .............................................................................................. 17-49
Power Management Capabilities (PCICO_PMC) ................................................................................ 17-50
Power Management Control/Status Register (PCICO_PMCSR) ........................................................ 17-50
PMCSR PCI-to-PCI Bridge Support Extensions (PCICO_PMCSRBSE) ............................................ 17-51
PCI Data Register (PCICO_DATA) ..................................................................................................... 17-52
Bridge
Options 2 Register (PCICO_BRDGOPT2) .............................................................................. 17-52
Power Management State Change Request Register (PCICO_PMSCRR) ........................................ 17-54
Error
Handling ............................................................................................................................................. 17-55
PLB Unsupported ,Transfer Type ....................... ............. .............................. ........... ............................... 17-55
PCI Master Abort .................................................................................................................................... 17-55
Bridge
PCI Master Receives Target Abort While PCI Bus Master .......................................................... 17-56
PCI Target Data Bus Parity Error Detection ........................................................................................... 17-57
PCI Master Data Bus Parity Error Detection ........................................................................................... 17-57
PCI Address Bus Parity Error While PCI Target ..................................................................................... 17-58
PLB Master Bus Error Detection ............................................................................................................. 17-58
PCI Bridge Clocking Configuration .............................................................................................................. 17-59
PCI Power Management Interface .............................................................................................................. 17-59
Capabilities and
Power Management Status and Control Registers ...................................................... 17-59
Power State Control ................................................................................................................................. 17-59
Changing
Power States .......................................................................................................................... 17-60
PCI Bridge Reset and Initialization .............................................................................................................. 17-61
Address Map
Initialization ....................................................................................................................... 17-61
Other Configuration Register Initialization .............................................................................................. 17-63
Target Bridge
Initialization ...................................................................................................................... 17-63
Local Processor Boot from PCI Memory ................................................................................................. 17-64
Type
° Configuration Cycles for Other Devices ...................................................................................... 17-64
Timing Diagrams ......................................................................................................................................... 17-64
PCI Timing Diagr9.m Descriptions .........................................................................................
~
................. 17-65
PCI Master Burst Read From SDRAM ............................................................................................... 17-65
PCI Master Burst Write To SDRAM ................................................................................................... 17-65
xlv
PPC405GP User's Manual Preliminary
To Next Page
Loading...
