CPU Read From PCI Memory Slave, Nonprefetching ........................................................................ 17-65
CPU Read From PCI Memory Slave, Prefetching .............................................................................. 17-65
CPU Write To PCI Memory Slave ....................................................................................................... 17-65
PCI Memory
To
SDRAM DMA Transfer ............................................................................................. 17-66
SDRAM
To
PCI Memory DMA Transfer ............................................................................................. 17-66
Asynchronous .......................................................................................................................................... 17-66
Synchronous ........................................................................................................................................... 17-92
. Chapter 18. Direct Memory Access Controller .................................................................. 18-1
External Interface Signals .............................................................................................................................. 18-1
Functional Overview ...................................................................................................................................... 18-2
Peripheral Mode Transfers
..
............................. ............... ....... ............. ............... ....
...
........ ............... ... ...... 18-2
Memory-to-Memory Transfers ................................................................................................................... 18-3
Scatter/Gather Transfers ....... ......... ...... .... ........ ........ ....... ................. ...... ............. ......... ..... ............ ....... ..... 18-4
Configuration and Status Registers .... ........... ............. ............. ............. ................ .................. ....... .... ............ 18-4
DMA
Polarity Configuration Register (DMAO_POL) .................................................................................. 18-5
DMA
Sleep Mode Register (DMAO_SLP) .................................................................................................. 18-6
DMA Status Register
(DMAO_SR)
..
.... ....................... ................ ................ ................
...
....... ......... ............ 18-7
DMA
Channel Control Registers (DMAO_CRO-DMAO_CR3) ................................................................... 18-8
DMA Source Address Registers
(DMAO_SAO-DMAO_SA3) ................................................................... 18-10
DMA Destination Address Registers (DMAO_DAO-DMAO_DA3) ............................................................ 18-11
DMA Count Registers
(DMAO_CTO-DMAO_CT3) ................................................................................... 18-11
DMA Scatter/Gather Descriptor Address Registers
(DMAO_SGO-DMAO_SG3) .................................... 18-12
DMA Scatter/Gather Command Register
(DMAO_SGC) . .... ....... ..... ........ .......... ..... .......................... ... .... 18-13
Channel Priorities. ........................
...
.... ................................................... ................ ............ .................... ...... 18-13
Data
Parity During DMA Peripheral Transfers ............................................................................................. 18-14
Errors ........................................................................................................................................................... 18-14
Address
Alignment Error
..
..... ....................... .......................... ............. .......................... .... ...................... 18-14
PLB Timeout ....... ... ..... ........... ................. ........... ......... ............ .... ............... ........... ........ .............. .... ......... 18-15
Slave Errors
..
..... ....... .... ..................... .......... ...... .......... ........... ............. ......... ...... ........... ............. ...... ... .... 18-15
DMA
Interrupts ............................................................................................................................................. 18-15
Scatter/Gather Transfers ................ .... ............. ...... .............. ....... .... .... ..... .............. ..... ................. ..... .... ... .... 18-16
Programming the DMA Controller ................................................................................................................ 18-17
Peripheral Mode Transfers
..
............................................ ................ .......................
...
.................... .......... 18-17
Memory-to-Memory Transfers ............. ................................ .............................................. ... ......... ..........
18-20
Software-Initiated Memory-to-Memory Transfers (Non-Deviced Paced) ................................................ 18-21
Chapter 19. Ethernet Media Access Controller .................................................................
19-1
EMAC Features ............................................................................................................................................. 19-2
EMAC Operation .... ............... ..... ............ ................ ....... ....... ......... ...... ....... ............... ...... ............ .... ......... ...... 19-3
MAL
Slave Logic ................... .............. ............................ .... ............ .... ............ ....... .......................... .... ..... 19-4
OPB Slave Logic ........ ......... ................................................ ........... ............. ...... ......... ....... ......... ....... ........ 19-4
Ethernet Address Match Logic ............................................ ............ ....... ............ .... ....................... ....... ..... 19-4
Configuration and Status Registers...... ................ ............................... .............. ................ ................ .... .... 19-4
Wake
On LAN Logic ....... ......... ........ ............. ..... ......... ......... ........ ..... ......................... ........ ............ ............ 19-4
Ethernet MAC
..
........... .................. ........ ...... ................ ............ .................................................. ..... ........ .... 19-5
EMAC Loop-Back Modes ........... ...... .... .... ............... ............... ....................................... .... .... ......... ........... 19-5
EMAC Transmit Operation .......... ...... .............. .......
...
....... ........... .... ................ .......................... ...... .... ........... 19-5
Arbitration Between
TX
Channels ......................................................................................... , ................... 19-6
Independent Mode .................................................................................................................................... 19-6
Dependent Mode .... .... ......... .... ........................................ ........ ....... ...... ............... .......... ....... ...... ............... 19-6
MAL
TX
Descriptor Control/Status Field ............................................................................................... 19-7
Early Packet Termination in Transmit ................................................................................................... 19-9
Empty
Packets .............................................................................................................................. ........ 19-9
Automatic Retransmission of
Collided Packets .............. ............. ................. ..... .................... ...... ......... 19-9
Inter-Packet Gap (IPG) Tuning ............................................................................................................. 19-9
Full-Duplex Operation
..
...
................ .............. ...... ............... ....................................................... ........ .... 19-9
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