IBM PowerPC 405GP - Page 19

MAL Registers ..... ........... .......... ........ ....... ........... .... ........................... ..................... ...... .......... ......... ....... ..... 20-24
MAL Configuration Register (MALO_CFG) ............................................................................................. 20-25
Channel Active Set and Reset Registers ......... ...... ..... ...... ....... ........ ..... ..... ......... ...... .... ..... ......... ......... ... 20-26
End of Buffer Interrupt Status Registers
.. .... ................. ............ ...... ........ ..... ........ ....... ..... ..... .... .......... 20-28
Error Registers . ..... ............ ......... ................... ....... ......... .... ........... ................ ..... .................... ....... ....... ........ 20-29
MAL Error Status Register (MALO_ESR) ....... ...... ....... ...... .......
... ... ... .... ...... ......... .... .......... .................. ... 20-29
MAL Interrupt Enable Register (MALO_IER) ........................................................................................... 20-31
Descriptor Error Interrupt Registers (MALO_ TXDEIR, MALO_RXDEIR) ................................................. 20-32
Channel Table
Pointer Registers (MALO_ TXCTPxR, MALO_RXCTPOR) ............................................... 20-33
Chapter 21. Serial Port Operations ..................................................................................... 21-1
Functional Description .................................................................................................................................... 21-1
Serial Input Clocking ...................................................................................................................................... 21-2
UART Registers ............................................................................... .............................................................. 21-4
Receiver Buffer Registers (UARTx_RBR) ................................................................................................ 21-5
Transmitter Holding Registers (UARTx_ THR) .......................................................................................... 21-5
Interrupt Enable Registers (UARTx_IER) ................................................................................................. 21-5
Interrupt Identification Registers (UARTx_IIR) .......................................................................................... 21-6
FIFO Control Registers (UARTx_FCR) ..................................................................................................... 21-7
Line Control Registers (UARTx_LCR) ...................................................................................................... 21-8
Modem Control Registers (UARTx_MCR) .............................................................................................. 21-10
Line Status Registers (UARTx_LSR) ...................................................................................................... 21-11
Modem Status Registers (UARTx_MSR) ................................................................................................ 21-13
Scratchpad Registers (UARTx_SCR) ..................................................................................................... 21-13
Divisor Latch LSB and MSB Registers (UARTx_DLL, UARTx_DLM) ..................................................... 21-14
FIFO Operation ............................................................................................................................................ 21-15
Interrupt Mode ......................................................................................................................................... 21-15
Receiver ............................................................................................................................................. 21-15
Transmitter ......................................................................................................................................... 21-16
Polled Mode ............................................................................................................................................ 21-16
UART and Sleep Mode ................................................................................................................................ 21-16
DMA Operation ............................................................................................................................................ 21-17
Chip Control Register
0 (CPCO_CRO) .................................................................................................... 21-17
Transmitter DMA Mode ........................................................................................................................... 21-18
Receiver DMA Mode ................................................................................................................................ 21-20
Chapter 22. IIC Bus Interface ......................................................................................... ~ .... 22-1
Addressing ..................................................................................................................................................... 22-1
Addressing Modes .................................................................................................................................... 22-1
Seven-Bit Addresses ............ ...... ........ .... .................. ........ .... ...... ........ .... .............. ..... .........
... ............. ...... 22-2
Ten-Bit Addresses .................................................................................................................................... 22-2
IIC Registers ................................................................................................................................................... 22-2
IIC Register Descriptions ............................................................................................................................... 22-3
IICO Master Data Buffer ............................................................................................................................ 22-3
IICO Slave Data Buffer ........ .............. .................... ..... ................................ ..... ........ ........ ............... ........... 22-4
IICO Low Master Address Register ........................................................................................................... 22-5
IICO High Master Address Register ........ .......... ....... ........ ....... ..... ....... .................. ..... ..... ......... ...... ........... 22-6
IICO Control Register ..................... ................. ......... ............. ....... ....... ......... ..... ...... ..... ..... ..... ............. ...... 22-6
IICO Mode Control Register ...................................................................................................................... 22-8
IICO Status Register ................................................................................................................................ 22-10
IICO Extended Status Register ................................................................................................................ 22-11
IICO Low Slave Address Register ........................................................................................................... 22-14
IICO High Slave Address Register .......................................................................................................... 22-14
IICO Clock Divide Register ....................................................................................................................... 22-15
IICO Interrupt Mask Register ................................................................................................................... 22-16
IICO Transfer Count Register .................................................................................................................. 22-17
IIca Extended Control and Slave Status Register ... ... .... ................ ..................... ..... ....... ...... ..... ............ 22-18
xviii PPC405GP User's Manual
Preliminary