17.5.2.2
PMM
0 Mask/Attribute Register (PCILO_PMMOMA)
PCILO_PMMOMA controls the size and attributes of the PLB space mapped to PCI memory for
range
O.
MASK
ENA
...
...
1
31
12
1
1
3
t
PRE
Figure 17-8.
PMM
0 Mask/Attribute Register (PCILO_PMMOMA)
31:12 MASK
The mask bits determine the size of the The mask must be of the form
111
.... 0000.
address map range.
Bits set to 1 cause the corresponding
PCILO_PMMOLA bits to
be
compared with
incoming
PLB addresses. Note that the
minimum range size is 4KB, and
valid
ranges are powers of
2.
For example, a
128MB range
would be encoded as
OxF8000 and a 4KB range would be
encoded as
all ones.
11:2
Reserved Returns
0 when read.
1
PRE Read Prefetching Enable
If read prefetch is enabled, the PCI bridge
1 Read prefetching is
enabled. prefetches 64 bytes from PCI memory
in
response to a PLB single-beat, byte-burst,
or
half word burst read from PMM
O.
0
ENA
PLB to PCI Memory Mapping Enable Note that PCILO_PMMOLA,
1 Memory mapping is enabled. PCILO_PMMOPCIHA, and
PCILO_PMMOPCILA must be initialized
before enabling.
17.5.2.3
PMM
0
PCI
Low
Address Register (PCILO_PMMOPCILA)
PCILO_PMMOPCILA defines the low-order 32 bits of the PCI address generated in response to a PLB
access to range
0. Only bits that are 1
in
PCILO_PMMOMA are passed to the PCI address. The other
(least significant) bits of the
PCI address are passed through from the PLB address. Only bits
31
:12
are writable. Bits
11
:0 are always
O.
17-22 PPC405GP User's Manual
Preliminary
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