Table 4-2. Data Cache Organization ................................................................................................................ 4-6
Table 4-3.
Priority Changes With Different Data Cache Operations .............................................................. 4-17
Table
5-1
..
Examples of Store Data Bypass ..................................................................................................... 5-4
Table 5-2.
OCM DCRs ...................................................
~
................................................................................. 5-5
Table 6-1. TLB Fields Related to
Page Size ................................................................................................... 6-4
Table 6-2.
Protection Applied to Cache Control Instructions ......................................................................... 6-15
Table 7-1. Clock Strapping Values .................................................................................................................. 7-3
Table 7-2.
PLL Tuning Settings ........................................................................................................................ 7-4
Table 7-3.
Possible Clocking Ratios for Reference Clock of 33.3MHz ............................................................ 7-5
Table 7-4.
Possible Clocking Ratios for Reference Clock of 25MHz ............................................................... 7-6
Table 7-5.
Possible Clocking Ratios for Reference Clock of 41.6MHz ............................................................ 7-7
Table 7-6. Example Synchronous
PCI Clock Frequencies
in
Asynchronous Mode ......................................... 7-8
Table 7-7. Clocking Control Registers .............................................................................................................. 7-9
Table 8-1.
MSR Contents after Reset .............................................................................................................. 8-3
Table 8-2.
SPR Contents After Reset .............................................................................................................. 8-4
Table 8-3. DCR Contents After Reset ............................................................................................................. 8-4
Table 8-4.
MMIO Register Contents After Reset ............................................................................................. 8-8
Table 9-1. Multiplexed
Pins ............................................................................................................................. 9-3
Table
10-1. UIC Interrupt Assignments .........................................................................................................
10-1
Table 10-2. UIC DCRs .................................................................................................................................... 10-3
Table 10-3. Interrupt Handling Priorities ...................................................................................................... 10-25
Table 10-4. Interrupt Vector Offsets ............................................................................................................ 10-27
Table 10-5. ESR Alteration by Various Interrupts ........................................................................................ 10-33
Table 10-6. ESR Alteration by Various Interrupts ........................................................................................ 10-33
Table 10-7. Register Settings during Critical Input Interrupts ...................................................................... 10-35
Table 10-8. Register Settings during Machine Check-Instruction Interrupts ............................................. 10-36
Table 10-9. Register Settings during Machine
Check-Data
Interrupts ...................................................... 10-36
Table 10-10. Register Settings during Data Storage Interrupts ................................................................... 10-37
Table 10-11. Register Settings during Instruction Storage Interrupts .......................................................... 10-38
Table 10-12. Register Settings during External Interrupts ........................................................................... 10-39
Table 10-13. Alignment Interrupt Summary ................................................................................................. 10-39
Table 10-14. Register Settings during Alignment Interrupts ........................................................................ 10-40
Table 10-15. ESR Usage for Program Interrupts ........................................................................................ 10-40
Table 10-16. Register Settings ,during Program Interrupts .......................................................................... 10-41
Table 10-17. Register Settings during System Call Interrupts .....................................................................
10-41
Table 10-18. Register Settings during Programmable Interval Timer Interrupts ......................................... 10-42
Table 10-19. Register Settings during Fixed Interval Timer Interrupts ........................................................ 10-42
Table 10-20. Register Settings during Watchdog Timer Interrupts ............................................................. 10-43
Table 10-21. Register Settings during Data TLB Miss Interrupts ................................................................ 10-43
Table 10-22. Register Settings during Instruction TLB Miss Interrupts ...............................
~
....................... 10-44
Table 10-23. SRR2 during Debug Interrupts ................................................................................................ 10-45
Table 10-24. Register Settings during Debug Interrupts ............................................................................. 10-45
Table 11-1. Time Base Access ...................................................................................................................... 11-3
Table 11-2.
FIT Controls ................................................................................................................................ 11-5
Table 11-3. Watchdog Timer Controls ........................................................................................................... 11-6
Table 12-1. JTAG Connector Signals ............................................................................................................ 12-2
xlii
PPC405GP User's Manual Preliminary
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