IBM PowerPC 405GP

Table 12-2. JTAG Instructions ........................................................................................................................ 12-3
Table 12-3.
RISCTrace Header Pin Description ............................................................................................ 12-5
Table 12-4. Debug Events ............................................................................................................................ 12-16
Table 12-5. DAC Applied to Cache
Instructions .......................................................................................... 12-20
Table 12-6.
Setting of DBSR Bits for DAC and DVC Events ........................................................................ 12-22
Table 12-7. Comparisons Based
on DBCR1[DVnM] .................................................................................... 12-23
Table 13-1.
CPM Registers ............................................................................................................................. 13-1
Table 14-1. DCRs Used to Access the Decompression Controller Registers ............................................... 14-4
Table 14-2.
Offsets for Decompression Controller Registers ........................................................................ 14-4
Table 15-1.
SDRAM Signal Usage and State During/Following Reset.. ......................................................... 15-2
Table 15-2.
SDRAM Controller DCR Addresses ............................................................................................ 15-2
Table 15-3.
SDRAM Controller Configuration and Status Registers ............................................................. 15-3
Table 15-4.
SDRAM Addressing Modes ......................................................................................................... 15-7
Table 15-5.
SDRAM Page Size ...................................................................................................................... 15-7
Table 15-6. Logical Address Bit on BA
1:0 and MemAddr12:0 Versus Addressing Mode .............................. 15-8
Table 15-7.
SDRAM Memory Timing Parameters ........................................................................................ 15-10
Table 15-8. Additional Latency when using ECC .......................................................................................... 15-14
Table 16-1. EBC
Signal Usage and State During/Following a Chip or System Reset.. .................................. 16-2
Table 16-2. Effect of Driver Enable
Programming on EBC Signal States ....................................................... 16-5
Table 16-3. External Master Arbitration ...................................................................
: ................................... 16-18
Table 16-4.
Signal States During Hold Acknowledge (HoldAck=1) .............................................................. 16-18
Table 16-5. EBC DCR Addresses ................................................................................................................. 16-23
Table 16-6. External Bus Configuration and
Status Registers ..................................................................... 16-23
Table 17-1.
PowerPC, CoreConnect PLB, and PCI Address Bit-Naming Conventions ................................. 17-3
Table 17-2.
PowerPC, CoreConnect PLB, and PCI Data Bus Bit-Naming Conventions ............................... 17-3
Table 17-3.
PLB Address Map ...................................................... : ................................................................ 17-6
Table 17-4.
PCI Memory Address Map ............................................................................................................ 17-8
Table 17-5. Transaction Mapping:
PLB -> PCI .......................................................................................... 17-10
Table 17-6. Transaction Mapping:
PCI--7 PLB ........................................................................................... 17-14
Table 17-7. Collision Resolution ................................................................................................................... 17-19
Table 17-8. Directly Accessed
MMIO Registers .......................................................................................... 17-19
Table 17-9.
PCI Configuration Address and Data Registers ....................................................................... 17-20
Table 17-10.
PCI Configuration Register Offsets ......................................................................................... 17-20
Table 17-11.
PLB Unsupported Transfer Types ........................................................................................... 17-55
Table 17-12. Address Map Register Values ................................................................................................ 17-63
Table 18-1. DMA Controller Externall/Os ......................................................................................................
18-1
Table 18-2. DMA Controller Configuration and Status Registers .................................................................. 18-4
Table 18-3. DMA Transfer
Priorities ............................................................................................................. 18-13
Table 18-4. Address Alignment Requirements ............................................................................................. 18-15
Table 18-5. Scatter/Gather Descriptor Table ................................................................................................ 18-16
Table 18-6. Bit Fields in the Scatter/Gather Descriptor Table ...................................................................... 18-16
Table 18-7. DMA Registers Loaded from Scatter/Gather Descriptor Table .................................................. 18-17
Table 19-1.
FCS/SA Enable - Possible Configurations ................................................................................. 19-11
Table 19-2.
FCS/Pad Enable - Possible Configurations .................................................... : .......................... 19-11
Table 19-3.
FCSNLAN Tag Enable - Possible Configurations ..................................................................... 19-11
Table 19-4.
In Range Length Error Behavior for Various Packet Lengths .................................................... 19-13
Preliminary
Tables
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