continues the receive process and allows the received packet to contain up to 1522 octets. Otherwise,
the receive process is continued
unless the length is greater than 1518 bytes.
19.6.3 Address Match Mechanism
The address match (or filtering) mechanism is a hardware aid that reduces the average amount of
CPU cycles required to determine whether an incoming packet
should be accepted.
EMAC uses various address
filters for incoming packets by using the following address recognition
modes.
• Individual mode (also referred to as physical)
• Multicast
mode (also referred to as group)
• Broadcast mode (an all-ones group address)
• Promiscuous mode
• Promiscuous multicast mode
• WOL mode
A
flowchart for address recognition of received packets is shown
in
Figure 19-13 on page 19-22. If the
least significant bit (LSb) of the first byte of the destination address (DA) is
0,
the packet is considered
individual. If the first bit received is 1, the packet is considered multicast. When the DA field contains
all 1 s, the packet is broadcast, a special type of multicast.
19.6.3.1 Non-WOL
Mode
When EMAC operates
in
single individual mode (EMACO_RMR[IAE] = 1), the DA of the received
packet is compared to the
physical address stored
in
the Individual Address High register
(EMACO_IAHR) and Individual Address Low (EMACO_IALR) register.
When EMAC operates
in
multiple individual mode (EMACO_RMR[MIAE] = 1), EMAC performs a
calculation on the contents of the DA field (logical address filter) to determine whether
or
not to accept
the packet.
When EMAC operates
in
promiscuous mode (EMACO_RMR[PME] = 1), all properly formed packets
are received,
regardless of the content of the DA field.
When EMAC operates
in
multicast promiscuous mode (EMACO_RMR[PMME] = 1), all multicast
packets are received, regardless of the content of the DA field.
When EMAC operates
in
broadcast address mode (EMACO_RMR[BAE] = 1), EMAC performs an
address compare on received packets with broadcast addresses.
When EMAC operates
in
multicast address mode (EMACO_RMR[MAE] = 1), EMAC performs a
calculation on the contents of the DA field (logical address filter) as
in
multiple individual mode,
in
order
to
determine whether or not the packet should be accepted.
The
logical address filter hardware is an implementation of a hash code searching technique
commonly used by software programmers. The hardware maps the DA of the incoming packet into
one of the 64 categories that correspond to 64 bits stored in the
EMACO_IAHT1-EMACO_IAHT 4 or
EMACO_GAHT1-EMACO_GAHT4 registers. The hardware accepts
or
rejects the packet, depending
on the state of the corresponding bit in the
EMACO_IAHT1-EMACO_IAHT4
or
EMACO_GAHT1-
EMACO_GAHT4 registers that corresponds to the
selected category.
19-20 PPC405GP User's Manual Preliminary
To Next Page
Loading...
Need help?
General
