Figure 19-14 on page 19-23 shows the details of the hardware mapping algorithm. The example
depicts multiple individual address mode, but with changes can be used for the multicast address
mode.
If the most significant bit of an incoming address is a
0,
the address is individual and is passed to the
individual address filter. If the most significant bit of an incoming address is a
1,
the address is
multicast and is passed to the multicast address filter. The individual/multicast address filter is a 64-bit
mask composed of
EMACO_IAHT1-EMACO_IAHT4 or the EMACO_GAHT1-EMACO_GAHT4
registers (each register contains 16 bits of a 64-bit mask). The incoming address is sent through the
FCS circuit. After the 48 address bits have gone through the FCS circuit, the high-order six bits of the
resulting FCS (32-bit CRC) are used to select one of the 64-bit positions in the individual/multicast
address filter. If the selected filter bit is a
1,
the address is accepted.
Note: The
individual/multicast address filter ensures only that there is a possibility that the incoming
packet
belongs to this node.
To
determine if the packet belongs to the node, the incoming
individual/multicast address propagated to the main memory is compared by software to the
list of logical addresses to be accepted by this node.
For software, the task of mapping an
individual/multicast address to one of 64 bit positions requires a
program that uses the same
CRC algorithm to calculate the hash.
Preliminary
Ethernet Media Access Controller
19-21
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