1
0
251
26
3
1
1
Figure 19-31. inter-Packet Gap Value Register (EMACO_IPGVR)
1
0
:
25
I
Reserved
19.7.18 STA Control Register (EMACO_STACR)
The EMACO_STACR controls the Mil Management interface. The software must follow the following
steps during access to the EMACO_STACR:
1 . Software polls EMACO_STACR[OC], waiting for it to be set by EMAC.
EMAC
sets EMACO_STACR[OC] = ° when the EMACO_STACR is written to.
EMAC then sets EMACO_STACR[OC] = 1 to indicate that the data has been written to the PHY,
or
the data read from the PHY is valid. The device driver should poll for EMACO_STACR[OC] = 1
before issuing a new command,
or
before using data read from the
PHY.
2. The software can perform read/write access to the EMACO_STACR.
3. EMAC clears EMACO_STACR[OC] (sets EMACO_STACR[OC] = 0) and starts activity on the
Mil
management interface.
4. Return to step 1.
PHYD
PHYE
OPSC
PRA
1
0
*
15116117118
1912021122
* t
26127
...
3
1
1
t
PCDA
Figure 19-32. STA Control Register (EMACO_STACR)
0:15 PHYD PHY data
Data to be sent to the
PHY if the command
is a write,
or
data is read from the PHY if
the command is a read.
16
OC
Operation Complete
o EMACO_STACR is addressed
1
PHY data transfer complete
17
PHYE
PHY
Error EMACO_STACR[PHYEl = 0 when a read is
o Successful read transaction
successful.
1 Read transaction was not successful
18:19 STAC STA Command EMAC sets EMACO_STACR[STAC] = 0
00
Reserved
when the command is
completed.
01
Read
10 Write
11
Reserved
Preliminary Ethernet Media Access Controller
19-39
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