20:21 OPBC
OPB Bus Clock Frequency EMACO_STACR[OPBC] is used to
0050
MHz
generate the Management Data
Clock
01
66 MHz
(EMCMDClk.
1083
MHz
When the
operational frequency differs
11
100 MHz
from those
in
the list, then the next greater
frequency
should be chosen.
22:26
PCDA
PHY Command Destination Address
27:31
PRA PHY Register Address
19.7.19 Transmit Request Threshold Register (EMACO_TRTR)
The EMACO_ TRTR defines the conditions that cause EMAC to initiate transmission to the Ethernet
MAC
sub-block, and for requesting service from
MAl.
EMACO_ TRTR[TRT] defines the number
of
occupied entries in the Transmit FIFO that should be
written before the Transmit
FIFO control logic initiates a transmit request to the Ethernet MAC sub-
block.
If
an entire packet is already located in the Transmit FIFO, then EMAC initiates a transmit regardless
of
the programmed value.
The software must coordinate the value
of
EMACO_ TRTR[TRT] with the Transmit FIFO size specified
in
EMACO_MR1 [TFS].
To
avoid deadlock, the sum of the Transmit Low Request (Figure 19-18 on page 19-28, bits 0:4) and
EMACO_ TRTR[TRT] must be smaller, by at least four, than the chosen size of the Transmit FIFO
specified in EMACO_MR1 [TFS].
To
avoid an underrun, program this threshold to a high enough value.
In
half-duplex mode,
in
case of collision, to allow packet re-transmission without involving MAL, EMAC
preserves the necessary space in the Transmit
FIFO unless it gets an indication that the collision
window has elapsed.
The EMACO_ TRTR may only be written to while EMACO_MRO[TXI] =
1.
19-40 PPC405GP User's Manual
Preliminary
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