• Hard Reset. When RESET input is asserted, EMAC aborts all on-going activities unconditionally,
initializes all internal state machines, counters, registers, and flushes transmit and receive FIFOs.
To
be recognized, the reset signal must be asserted for at least two cycles of the slowest clock
domain inside EMAC (indicating that the hard reset must be at least 800 ns).
• Soft Reset. Software first should reset the appropriate MAL channels and then begin a soft reset by
setting
EMACO_MRO[SRST] =
1.
In response to the soft reset, EMAC aborts all on-going activities
unconditionally,
initializes all internal state machines, counters, registers, and flushes transmit and
receive
FIFOs. After EMAC finishes all activities related to the soft reset processing,
EMACO_MRO[SRST] =
o.
• Smart Reset. The software initializes smart reset mode by writing 0 to EMACO_MRO[TXE]
or
EMACO_MRO[RXE],
or
to both. In this case, the Ethernet MAC SUb-block completes on-going
activity (receive, transmit, or both) and then goes to the
related Idle state (indicated by setting
either
EMACO_MRO[TXI] = 1
or
EMACO_MRO[RXI] =
1,
or
both). In this case, the control logic sub-
block of EMAC is still accessible for OPB and MAL transactions.
Before performing the necessary configuration changes
in
EMAC, the software must follow one of the
following scenarios. Then the EMAC can be properly configured.
19.10.1.2 Scenario 1
• Hard/soft reset was activated.
• During hard/soft reset, EMACO_MRO[TXE] and EMACO_MRO[RXE] are reset.
• Software detects that the EMACO_MRO[SRST] is reset (after soft reset only).
•
Software keeps EMACO_TMRO[GNPO, GNP1] =
o.
• The software can change one or more fields
in
registers marked with a Reset write access mode
in
Table 19-5, "EMAC Register Summary," on page 19-23 (actually, all EMAC registers are accessible
in
this scenario).
• The software initializes EMACO_ TMRO[GNPO, GNP1] as appropriate.
• The software configures EMACO_MRO[TXE, RXE].
19.10.1.3 Scenario 2
• Software sets EMACO_MRO[TXE] =
o.
• The TXMAC component of the Ethernet MAC sub-block completes on-going activity and then sets
EMACO_MRO[TXI] = 1 to enter the related Idle state.
• Software detects EMACO_MRO[TXI] =
1.
• Software performs the necessary EMAC configuration, keeping EMACO_MRO[TXE] =
o.
The
software can access
only part of the EMAC registers marked with write access mode T
in
Table 19-5, "EMAC Register Summary," on page 19-23.
• After all configuration is done, software can set EMACO_MRO[TXE] = 1.
Note: When Scenario 2 occurs, EMAC can still receive packets if EMACO_MRO[RXE] = 1. Scenarios
2 and 3 can occur
simultaneously.
Preliminary Ethernet Media Access Controller 19-45
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