IBM PowerPC 405GP - Page 564

20.1.1 MAL - Internal Structure
Figure 20-2 illustrates the MAL internal structure.
RX TX
Common
Channel
Common
Channel
Logic Logic
RX
OPS
Master
EMAC
TX
Tx Channel
Handler
PLS OPS
Access
Arbiter
Figure 20-2. MAL Internal Structure
20.1.1.1 PLS Master
The PLS Master performs PLS transactions for MAL, and is used to transfer data between a
COMMAC and memory, fetch buffer descriptors, and communicate status regarding data transfer.
20.1.1.2 OPS Master
The OPS Master performs OPS transactions for MAL, and is used to transfer data between a
COMMAC and memory.
20.1.1.3 TX Channel Handler
The TX channel handler is a dedicated section for each TX channel. It keeps a record of the
descriptor information and the current state of each
channel.
20.1.1.4 RX Channel Handler
The RX channel handler is a dedicated section for each RX channel. It keeps a record of the
descriptor information and the current state of each
channel.
Preliminary Memory Access Layer 20-3