Figure
20-1
illustrates a general system structure overview of an embedded PowerPC processor core
integrated with a packet oriented communication core. For the PPC405GP, the sole
COMMAC is
EMAC.
PPC40S
Processor Core
Figure
20-1. General PPC405GP
Structure
(Overview)
COMMACs are configured and controlled by the processor core using the OPS without MAL
intervention. Packet data to be transmitted and received are stored
in
buffers
in
external memory. The
MAL processes buffer descriptors and provides
all data access facilities to the COMMACs.
The MAL is not aware of COMMACs such as EMAC as an entity. It is only aware of the COM MAC's
channels.
In
the PPC405GP, EMAC contains two
TX
channels and one RX channel. Transmit and
receive operations can be performed simultaneously by MAL
(full duplex). When a channel wins
arbitration, MAL transfers data between system memory and the
COMMAC. MAL and the software
driver maintain separate, dedicated buffer descriptor tables for each channel to maintain channel,
packet, and buffer status. Packets can be constructed from one data buffer,
or
several data buffers
(known as buffer chaining).
20-2 PPC405GP User's Manual Preliminary
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