Chapter 20. Memory Access Layer
The Memory Access Layer (MAL) is a hardware core that manages data transfers between packet-
oriented communications cores,
also known as COMMACs (communications media access
controllers), and memory.
In
the PPC405GP, MAL manages the transfer of packets between the
Ethernet Media Access
Controller (EMAC) and memory attached to the PPC405GP (SDRAM
or
SRAM). The primary function of MAL is to move packets directly between memory and a COMMAC
core to minimize involvement of the processor core.
MAL is comprised of
multiple transmit (TX) and receive (RX) channels, each of which is dedicated to
a specific
COMMAC
in
the chip.
In
the PPC405GP, the EMAC utilizes MAL TX channels 0 and
1,
and
MAL RX
channel
o.
To
communicate with software device drivers, MAL utilizes a buffer descriptor ring structure
in
memory. A software device driver uses the buffer descriptor structure to inform MAL about buffer
locations and packet
or
buffer status. MAL uses the buffer descriptors to convey packet transfer status
from the
COMMAC core back to the software device driver. Each MAL channel requires its own buffer
descriptor
table ring structure
in
memory.
MAL provides software device drivers a generic interface for
control of:
• Configuration sequence
• Activation commands
• Deactivation commands
• Memory status handling
20.1
MAL Features
• No restrictions on buffer alignment
• Aligned
bus accesses to enable burst operation with external memories
• Configurable receive buffer size (configurable per channel)
•
No minimum transmit buffer size
• Maximum buffer sizes of 4095 bytes (TX) and 4080 bytes (RX)
• Up to 256 descriptors
in
the buffer descriptor table per channel
•
Configures COM MAC according to commands specified
in
the descriptor status/control field
•
Updates the descriptor status/control field at the end of packet transfer according to the status
received from
COMMAC
•
Buffer-based interrupt capabiliti!3s for each channel
•
Concurrent operation of RX and
TX
channels
•
Configuration using Device Control Registers (DCRs)
• Programmable PLB arbitration priority
• PLB/OPB error detection
Preliminary
Memory Access Layer 20-1
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