20.6.5 TX
Status/Control
Field
Format
0 2
3
4
5
6
7
8 9
10
11
12 13
14 15
R W
I CM I
L
I Res I
I
I
*
I
* *
I
*
I
*
I
* *
I
*
I
*
I
*
I
"'-
/'-
/
V
V
MAL related data
COMMAC channel related data
* - COMMAC specific control
or
status fields
Figure
20-7. TX
Status/Control
Field
Note:
The bit numbering
in
Figure 20-7 relates to the Buffer Descriptor's fullword which contains both
the status/control and the
length fields.
20.6.5.1
Bit
0 - R - Ready
This bit is set by the device driver and is cleared by MAL.
The device driver sets this bit after preparing the buffer for transmission.
MAL
.clears this bit when finish processing the buffer descriptor. MAL doesn't clear the Ready bit
in
the case of backing-up a packet request and
in
case of continuous mode (see "Back Up a Packet for
Transmit" on page
20-10 and "Continuous Mode for Transmit" on page 20-10).
20.6.5.2
Bit
1 - W - Wrap
o - This is not the last data buffer descriptor
in
the buffer descriptor table.
1 - This is the last data buffer descriptor
in
the buffer descriptor table. After this buffer has been used,
MAL
will transmit data from the first descriptor buffer
in
the table.
This bit is controlled by software only. It controls MAL activities, and does not affect the COMMAC
channel.
20.6.5.3
Bit
2 -
CM
- Continuous Mode
o - Normal Operation
1 -
Contifluous Operation. After this buffer descriptor is closed, the R-bit is not cleared by MAL. This
ensures that the data buffer is ready for transmission when MAL next accesses this buffer descriptor.
However, the R-bit is
cleared if an error occurs during transmission.
This bit is
controlled by software only. It controls MAL activities and does not affect the COMMAC
channel.
20.6.5.4
Bit
3 - L - Last
o - This is not the last buffer
in
the current packet.
1 - This is the
last buffer
in
the current packet.
This bit is
controlled by software only. It controls MAL activities, and does not affect the COMMAC
channel.
Preliminary Memory Access Layer
20-15
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