20.6.5.5
Bit
4 - Reserved
This bit is reserved. It is assumed that this bit is set to zero by the software.
20.6.5.6
Bit
5 - I - Interrupt
1 - After finishing processing the current buffer, if this bit is
1,
the end of buffer field
in
the End of
Buffer
Interrupt Status Register is set and the end of buffer interrupt is asserted.
o - There is no action taken by MAL once it reaches the end of the current buffer.
MAL asserts the end of buffer interrupt after it updates the buffer descriptor's status
field.
This bit is controlled by software only. It controls the MAL activities and does not affect the COMMAC.
20.6.5.7 Bits 6
to
15
These bits are COMMAC specific and may contain control fields generated by the software in order to
control the COMMAC channel. They may also contain status fields, generated by the COMMAC
channel, that will be processed by software.
20.6.6 RX
Status/Control
Field
Format
o
2
3
4
5
6 7 8
9 10
11
12 13 14 15
~
____________
~7
MAL related data
COM MAC channel related data
* - COM MAC specific control
or
status fields
Figure
20-8. RX
Status/Control
Field
Note:
The bit numbering
in
Figure 20-8 relates to the buffer descriptor's fullword which contains both
the
status/control and the length fields.
20.6.6.1
Bit
0 - E - Empty
o - The data buffer associated with this buffer descriptor has been filled with received data, or data
reception has been aborted due to an error condition. Software is free to examine or write to any
fields of this buffer descriptor. While this bit is set to Not Empty, MAL will not use this buffer descriptor
again.
1 - The data buffer associated with this buffer descriptor is empty, or reception is currently
in
progress. This buffer descriptor and its associated receive buffer are owned by MAL. Once the E-bit is
set, software
should not write to any fields of this RX buffer descriptor.
MAL clears this bit after the buffer has been filled with received data
or
after an error is encountered.
Software sets this bit to Empty after preparing the buffer for reception. This bit
controls MAL and
software activities. See
"Bit
2-
CM - Continuous Mode" on page 20-17.
20-16
PPC405GP User's Manual Preliminary
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