Figure 20-10 on page 20-23 describes MAL actions once an error is detected. Note that the actual
decisions MAL makes may be
in
a different order than represented by this figure.
In
any case, the
device driver
should consider that all of the MAL actions are performed at the same time.
20.8 MAL Registers
Access
to
MAL registers is through the DCR interface.
• Unless otherwise specified, all register fields are initialized at chip reset to
O.
• Reserved fields are read as undefined and must be written as
Os.
Table 20-1.
MAL
Registers
Register
DCR
Number
Access
Description
MALO_CFG
Ox180 RIW Configuration Register
MALO_ESR
Ox181
R/Clear Error Status Register
MALO_IER
Ox182 RIW
Interrupt
Enable Register
MALDBR
Ox183 R Debug Register
MALO_ TXCASR
Ox184
RIW
TX
Channel Active Set Register
MALO_ TXCARR
Ox185
RIW
TX
Channel Active Reset Register
MALO_
TXEOBISR
Ox186
R/Clear
Tx
End of Buffer Interrupt Status Register
MALO_
TXDEIR
Ox187 R/Clear
Tx Descriptor Error
Interrupt Register
MALO_RXCASR
Ox190 RIW
RX Channel Active Set Register
MALO_RXCARR
Ox191
RIW
RX Channel Active Reset Register
MALO_RXEOBISR
Ox192
R/Clear Rx End of Buffer
Interrupt Status Register
MALO_RXDEIR
Ox193
R/Clear Rx Descriptor Error
Interrupt Register
MALO_
TXCTPOR
Ox1AO
RIW
Channel Tx 0 Channel Table Pointer Register
MALO_
TXCTP1 R
Ox1A1
RIW
Channel Tx 1 Channel Table Pointer Register
MALO_RXCTPOR
Ox1CO
RIW
Channel Rx 0 Channel Table Pointer Register
MALO_RCBSO
Ox1EO
RIW
Channel RX 0 Channel Buffer Size Register
20-24 PPC405GP User's Manual Preliminary
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