20.8.1 MAL Configuration Register (MALO_CFG)
This register defines the operational mode of MAL. Unless a configuration change is required during
system operation, the configuration register needs to be set
only during system initialization.
SR
...
GA
PLBLE
+ +
EOPIE
SD
+
...
t f t
PLBP
OA
PLBLT
161
17
1
18
281
2
913013
1
1
f
LEA
t
OPBBL
Figure 20-11. MAL Configuration Register (MALO_CFG)
0 SR
MAL Software Reset This bit is used to generate a general reset to
MAL
o MAL reset is complete through a software command.
1 Reset the MAL
After setting this bit, MAL hardware (registers,
interface and
internal state machines) returns to the
power-on reset
value.
The software writes 1 to this bit in order to drive
MAL to the reset state. The bit is cleared by the
hardware when the reset is
completed (one system
clock).
1 :7
Reserved
8:9
PLBP PLB Priority Determines the priority of MAL requests on the PLB.
00
Lowest
01
10
11
Highest
10
GA
Guarded Active
When this bit is set, MAL
applies the GUARDED
o GUARDED signal not signal to the PLB slave when it is the initiator on the
applied to the PLB slave bus.
1 GUARDED
signal applied
When set, the slave can access all the memory in
to the
PLB slave
the current page as well as the subsequent page.
11
OA Ordered Active
When this bit is set, MAL
applies the ORDERED
o ORDERED signal not signal to the PLB slave when
it
is initiator on the bus
applied to the PLB slave during data write transactions.
1
ORDERED signal applied
Note that the ORDERED signal is always driven
to the
PLB slave
active during status write transactions.
12
PLBLE PLB Lock Error
When this bit is set,
MAL
applies the LOCKERROR
o LOCKERROR signal not signal to the PLB slave when it is the initiator during
applied to the PLB slave PLB transactions.
1
LOCKERROR signal
applied
to the PLB slave
13:16 PLBLT PLB Latency Timer Determines the number of cycles allowed for burst
transactions on the
PLB.
17 PLBB PLB Burst When this bit is reset,
MAL
is not allowed to perform
o Burst transactions not burst transactions.
allowed
1 Burst transactions allowed
Preliminary
Memory Access Layer
20-25
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