24
OPBBL OPB Bus Lock When this bit is set, MAL locks the OPB during data
o OPB not locked
transfers to and from the COMMACs.
1 OPB locked
18:28
.........
Reserved
..•...
29
EOPIE End of Packet Interrupt When this bit is set, an interrupt is generated on
Enable
every end of packet (both transmit and receive).
o Generate interrupt on every When clear, end of packet/buffer interrupt is
end-of-packet
only if the generated only if the buffers I bit is set (1).
buffers
I bit is set Note:
An
interrupt is generated for every descriptor
1 Generate interrupt is on
on which the
I bit is set, regardless of the
everyend-of-packet
state of the
EOPIE bit.
30 LEA Locked Error Active Determines
MA~s
error handling mode. When this
o Handle errors
in
a non- bit is set, MAL will handle errors
in
the locked mode,
locked mode otherwise it will handle errors
in
a non-locked mode.
1
Handle errors
in
locked
mode
31
SD MAL Scroll Descriptor Determines whether or not MAL should scroll to the
o Do not scroll to the first first descriptor of the next packet, following an early
descriptor of the next
packet termination initiated by the related
packet COMMAC. When set, Scrolling mode is active.
1
Scroll to the first descriptor
of the next packet
20.8.2 Channel Active Set and Reset Registers
For the Channel Active Set/Reset Registers (MALO_ TXCASR, MALO_ TXCARR, MALO_RXCASR,
MALO_RXCARR), each bit represents its associated
channel (bit ° for channel
0,
etc.). When a bit is
equal to
1,
the channel has been enabled for operation. When a bit is equal to
0,
the channel is
disabled (MAL ignores any requests for service). If a channel is active when its enable bit is cleared,
MAL stops processing the current packet. After the channel's enable bit is cleared, MAL goes back to
the top of the
channel descriptor table (pointed to by the Channel Table Pointer Register).
•
To
enable a channel:
- Write a 1 to its corresponding bit
in
the Channel Active Set Register (CASR).
-
Multiple channels can be enabled with a single CASR register write.
•
To
stop and reset a channel:
-Write
a 1 to its corresponding bit
in
the Channel Active Reset Register (CARR).
- Writing a
° to bits
in
the CARR registers has no effect on the channels.
- Multiple channels can be reset with a single CARR register write.
MAL
also clears the enable bit of a channel following an indication of an error on the channel. The
CASR or CARR register(s) can be read to determine which
channels are currently active. The
following figures describe these registers.
20-26
PPC405GP User's Manual Preliminary
To Next Page
Loading...
