IBM PowerPC 405GP - Page 592

16:26
Reserved
27
DEI
Descriptor Error Interrupt A descriptor data error is recognized
o No error
during access to the descriptor table.
1 Descriptor data error recognized
This error indication is asserted when a
non-valid descriptor is accessed, which is
not the first descriptor in a TX packet. Set
condition for this bit generates a maskable
interrupt.
28
ONEI OPS Non-fullword Error Interrupt This bit is set following a non-fullword
o No error
acknowledgment coming from a slave. Set
1 Non-fullword acknowledgment from a
condition for this bit generates a
maskable
slave
interrupt.
29
OTEI
OPS Timeout Error Interrupt
This bit is set following an OPS time out
o No error
error indication. Set condition for this bit
1
OPS time-out
generates a maskable interrupt.
30 OSEI OPS Slave Error Interrupt
This bit is set following an OPS error
o No error indicated by the slave. Set condition for
1
OPS error from a slave
this bit generates a maskable interrupt.
31 PSEI
PLS Sus Error Interrupt This bit is set following a PLS error
o No error
indication (from the PLS slave). Set
1 PLS error indication
condition for this bit generates a
maskable
interrupt.
20.9.2 MAL Interrupt Enable Register (MALO_IER)
Each bit in the following register, when it is set, enables assertion of the interrupt signal
(MAL_SERR_INT)
when the related bit in the MALO_ESR (interrupt bit) is set.
NWE OPS
10
.. ..
f t f
DE TO PLS
Figure 20-19.
MAL Interrupt Enable Register (MALO_IER)
0:26 Reserved
27
DE
Descriptor Error
When set, this bit
enables the descriptor
error (descriptor not
valid) interrupt.
28 NWE Non_ W
_ErUnCEnable
When set, this bit enables OPS non-word
transfer error interrupt.
29
TO
Time_OuUnCEnable When set, this bit enables OPS time-out
error interrupt.
30
OPS
OPS_ErUnt_Enable
When set, this bit enables the OPS Slave
error interrupt.
31
PLS
PLS_ErUnt_Enable
When set, this bit enables the PLS error
interrupt.
Preliminary
Memory Access Layer 20-31