20.9.3 Descriptor Error Interrupt Registers (MALO_ TXDEIR, MALO_RXDEIR)
Each bit
in
the following registers is related to a channel descriptor buffer table. Each bit indicates a
descriptor data error
related to a certain channel.
The
TX Descriptor Error register contains the Descriptor errors bits of the
TX
channels. The RX
Descriptor Error register contains the Descriptor errors bits of the RX
channels. The mechanism (as
described
below) for both RX and
TX
registers is the same.
MAL sets a
channel's bit when a descriptor data error was recognized during access to the descriptor
table of a specific channel (see "Descriptor Error" on page 20-19).
The device driver resets the interrupt by writing a 1 to the
related bit. Writing a 0 has no effect. When
one or more of the
TX
Descriptor Error Interrupt bits is set, then the MAL_ TX_DESC_ERR_INT bit is
set. When one or more of the RX Descriptor Error
Interrupt bits is set, then the
MAL_RX_DESC_ERR_INT
signal is set (attached to UIC on the PPC405GP).
10
112
3
1
1
Figure 20-20. TX Descriptor Error Interrupt Register (MALO_ TXDEIR)
0:1
Transmit Descriptor Error Interrupt Each bit represents its
rel~ted
channel (bit 0 for channel
0,
etc.).
When one
or
more bits are set,
MAL_DESC_ERR_INT is set. Writing 1 to
a bit resets it.
There are
only two
TX
channels in the
PPC405GP.
2:31
I
Reserved
10
11
311
Figure 20-21.
RX
Descriptor Error Interrupt Register (MALO_RXDEIR)
0 Receive Descriptor Error Interrupt
Each bit represents its related
channel
(bit 0 for channel 0 etc.).
When one
or
more bits are set,
MAL_DESC_ERR_INT is set. Writing 1 to
a bit resets it.
There is
only one RX channel in the
PPC405GP .
1
:31
.
..
Reserved
20-32 PPC405GP User's ivianuai
Pislfminary'
To Next Page
Loading...
