IBM PowerPC 405GP - Page 594

20.9.4 Channel Table Pointer Registers (MALO_ TXCTPxR, MALO_RXCTPOR)
MAL uses RX Channel table pointer registers, one for each RX channel, and TX Channel table
pointer registers, one for each TX channel. The Channel Table Pointer Registers point to the base
address, in memory, of the descriptor buffer
table used by each channel.
Note 1: Bits 0 to 12 of all the TXCTPxR registers are mapped to the same physical register. Writing
into any of these registers overwrites the value of bits 0 to 12 in all the TXCTPxR registers.
Read operation has no effect. Bits
0 to 12 of all the RXCTPxR registers are mapped to the
same
physical register. Writing into any of these registers overwrites the value of bits 0 to 12
in all the RXCTPxR registers. Read operation has no effect.
Note 2: When changing the value of either of the MALO_ TXCTPxR registers, both TX channels must be
idle. To verify a channel is idle, check the device's Transmit Idle bit. Another way to assure that the
channels are idle is to disable the channels before changing the MALO_ TXCTPxR regsiter, and
then
re-enable them once the MALO_ TXCTPxR register is set to its new value.
The TX and RX Channel Table Pointer Registers have an identical format as shown in Figure 20-22
and Figure 20-23. There are two TX registers (0 and 1), and one RX register (0) in PPC405GP.
10
31
1
Figure 20-22. TX Channel Table Pointer x Register (MALO_ TXCTPxR)
0:31
Channel Table Pointer Pointer to the base address in memory of
the buffer descriptor table used by the
channel. The value entered should be a
pointer
to a location in memory
accommodating
an aligned double fullword
(this requires the three least significant bits
of this pointer must be 000).
There are two transmit channels (x = 0
and 1).
1
0
3
1
1
Figure 20-23. RX Channel Table Pointer x Register (MALO_RXCTPxR)
0:31
Chanl1el Table Pointer Pointer to the base address in memory of
the buffer descriptor table used by the
channel. The value entered should be a
pointer to a location in memory
accommodating
an aligned double fullword
(this requires the three least significant bits
of this pointer must be 000)
There is one receive channel (x = 0).
The Table Pointer Registers retain their value following Soft Reset or Channel Reset.
Preliminary Memory Access Layer 20-33