Chapter 21. Serial Port Operations
The PPC405GP contains two universal asynchronous receiver/transmitters (UARTs) which provide
two
full-duplex serial interfaces to support communications with serial peripheral devices. Each UART
is
compatible with the National Semiconductor (NS) 16550 chip, and includes a 16-byte send and a
16-byte receive
FIFO.
Features of the UART include:
• Compatible
with the NS 16550
•
16-byte send FIFO, 16-byte receive FIFO
• Full duplex
operation
• Programmable baud rate generator
• Supports 5- to 8-bit word size, 1
or
2 stop bits, even, odd,
or
no parity
• One 8-wire interface
(UARTO)
and one 4-wire interface (UART1)
The UART performs
serial-to-parallel conversion on data characters received from a peripheral
device, and parallel-to-serial conversion on data characters received from the processor. The
processor can read the
complete status of the UART at any time during the functional operation.
Status information reported includes the type and condition of the transfer operations being
performed by the
UART,
as well as any error conditions, such as parity, overrun, framing, and break
interrupt.
This UART is
functionally identical to NS16450
in
character mode (on power up it will be
in
this
mode), and can be put into
FIFO mode to relieve the processor of excessive software overhead.
Here,
internal FIFOs are activated allowing 16 bytes (plus 3 bits per byte of error data
in
the RCVR
FIFO) to be stored
in
both receive and transmit modes.
The source of the UART
serial clock input is selected
in
Chip Control Register 0
(CPCO_CRO[UOEC:U1 ECl)
bits 24 and 25. Either the internal serial clock
or
an external serial clock
can be selected. A programmable baud rate generator is included that is capable of dividing the
UART
serial clock input by a divisor of 1 to (2
16
- 1) and producing the 16x clock required for driving
the UART
internal transmitter/receiver logic. The internal serial clock input is derived from the CPU
clock
by a divisor specified
in
CPCO_CRO[UDIV].
The UART has an interrupt system that can be programmed to the user's requirements, helping to
minimize the computing required to
handle the communications link. UART interrupts are capable of
triggering an interrupt request to the
PPC405GP interrupt controller.
21.1
Functional Description
• Runs NS 16550 software
• Registers are identical to the NS 16550 register set
• After reset, all registers are identical to the NS16450 register set
.•
Complete status reporting capability
•
Transmitter and receiver are each buffered with 16-byte FIFOs when FIFO mode selected
Preliminary Serial Port Operations 21-1
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