• Can add/delete standard asynchronous communication bits such as start, stop, and parity to/from
the
serial data
• When in character mode, holding and shift registers eliminate the need for precise synchronization
between the processor and
serial data
• Full prioritized interrupt system controls
• Independently controlled
transmit, receive, line status, and data set interrupts
• Programmable baud rate generator divides the UART serial clock input by 1 to
(2
16
_1) and
generates the 16x
clock:
Baud rate (bps) = (Serial Clock Input) / (16 x Decimal Divisor)
• Receiver uses 5-way oversampling as follows: it samples each serial bit five times, and if at least
three of the samples are 1
's,
the bit is·determined to be a
1,
otherwise it is a 0
• Fully programmable
serial-interface characteristics:
- 5-, 6-, 7-, or 8-bit characters
- Even, odd, or no parity bit generation and detection
- 1-,1.5-, or 2-stop bit generation
-
Variable baud rate
• Line break generation and detection, and false start bit detection
• Internal diagnostic capability:
- Loopback controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
21.2 Serial Input Clocking
The two PPC405GP UARTs can be clocked individually from an external serial clock or from an
internally generated serial clock. The internally generated serial clock is derived from the CPU clock,
and is CPU/n, where n ranges from 1 to 32. The divisor n is programmed by setting a value of 0 to
31
in CPCO_CRO[UDIV] (see Chapter 7, "Clocking").
The choice of serial clock frequency affects the serial communications error rate. If an external clock
of 1.8432 MHz (or some multiple of this frequency) is used, the error rate approaches zero. However,
when using the
internally generated clock only certain clock frequencies are possible, which results
in
a small, non-zero error rate
in
all cases, unless SysClk is chosen as an integer multiple of
1.8432 MHz.
The optimum
serial clock frequency is determined from the following relationship:
Serial Clock
= Baud Rate x 16 x UART Divisor
Acceptable baud rates are always integral multiples of 300 (for example, 1200 = 4 x 300). Table
21-1
shows optimum UART divisor and CPU divide ratios for a range of possible baud rates. This
information is provided for four different CPU
clock frequencies. The UART divisor is programmed in
21-2
PPC405GP User's Manual Preliminary
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