IBM PowerPC 405GP - Page 598

UARTx_DLM and UARTx_DLL (see "Divisor Latch LSB and MSB Registers (UARTx_DLL,
UARTx_DLM)" on page
21-14). The value range is 1 to (2"16-1)=65535.
Table 21-1. Baud Rate Settings
Desired Baud
CPU:UART Serial Clock Actual Baud
Rate (bps) Divide Ratio Frequency (MHz) UART Divisor Rate (bps) Error (%)
CPU
Clock = 150MHz
1200 13 11.5380 601 1199.923205 0.0063996
2400
21
7.1429
186
2400.153610
0.0064004
4800
21
7.1429 93 4800.307220 0.0064004
9600
16 9.3750
61 9605.532787 0.0576332
19200
14 10.7140
35
19132.653061
0.3507653
28800
13 11.5380
25 28846.153846 0.1602564
33600
9 16.6670 31 33602.150538 0.0064004
38400
9 16.6670 27 38580.246914 0.4693930
57600
18 8.3333 9 57870.370370 0.4693930
115200
9 16.6670 9 115740.740741 0.4693930
307200 30 5.0000
1
312500.000000
1.7252604
CPU Clock = 166.66 MHz
1200 31
5.3763
280
1200.076800 0.0064000
2400
31 5.3763
140
2400.153600 0.0064000
4800
31 5.3763 70 4800.307200 0.0064000
9600
31 5.3763 35 9600.614401 0.0064000
19200
32 5.2083 17 19148.284237 0.2693529
28800
19 8.7719 19 28855.032202 0.1910840
33600
31 5.3763 10 33602.150403 0.0064000
38400
17 9.8039 16 38296.568474 0.2693529
57600 30
5.5556
6
57870.370139 0.4693926
115200 30 5.5556
3
115740.740278 0.4693926
307200
17
9.8039
2 306372.547794 0.2693529
CPU Clock = 200MHz
1200 11 18.1820 947
1199.961601
0.0031999
2400
28 7.1429 186 2400.153610 0.0064004
4800
28 7.1429 93 4800.307220 0.0064004
9600
14 14.2860 93 9600.614439 0.0064004
19200
31 6.4516 21 19201.228879 0.0064004
28800
31 6.4516 14 28801.843318 0.0064004
33600
31 6.4516 12 33602.150538 0.0064004
38400
25
8.0000
13 38461.538462 0.1602564
57600
31
6.4516
7 57603.686636
0.0064004
115200
12
16.6670 9
115740.740741 0.4693930
307200
20 10.0000
2 312500.000000
1.7252604
Preliminary Serial Port Operations 21-3