IBM PowerPC 405GP - Page 599

21.3 UART Registers
UART registers are accessed via memory locations OxEF60_0XYY where X=3 for UART 0 and X=4
for UART
1.
Table 21-2. UART Configuration Registers
UART Config Register Address
RIW
Description Reset
UARTx_RBR
EF60_0XOO 1
R
UART x Receiver Buffer Register
UARTx_THR
EF60_0XOO 1
W
UART x Transmitter Holding Register
UARTx_IER EF60_0X01
1
RIW
UART x Interrupt Enable Register
00000000
UARTx_"R
EF60_0X02
R
UART x Interrupt Identification Register
00000001
UARTx_FCR EF60_0X02
W
UART x FIFO Control Register 00000000
UARTx_LCR EF60_0X03
RIW
UART x Line Control Register
00000000
UARTx_MCR EF60_0X04
RIW
UART x Modem Control Register
00000000
UARTx_LSR EF60_0X05
RIW
UART x Line Status Register 01100000
UARTx_MSR EF60_0X06
RIW
UART x Modem Status Register xxxx 0000
UARTx_SCR EF60_0X07 RIW UART x Scratch Register
UARTx_DLL
EF60_0XOO 1
RIW
UART x Divisor Latch (LSB)
UARTx_DLM EF60_0X01
1
RIW UART x Divisor Latch (MSB)
1. UARTx_LCR[DLAB] controls the function accessed through registers EF60_0XOO and EF60_0X01. When
UARTx_LCR[DLAB] is 0, access is enabled to the ReceiverfTransmitter registers and the Interrupt Enable register.
When UARTx_LCR[DLAB] is a 1, access is enabled to the Divisor Latch registers.
The system programmer may access any of the UART registers via the processor. These registers
control
all UART operations including transmission and reception of data. In PPC405GP there are two
UARTs, designated
0 (S-wire interface) and 1 (4-wire interface). In the following sections, the registers
are specified with a generic name where x represents
0 or 1. For example, the Line Control Register
appears as a UARTx_LCR.
For
UART1 , two of the four wires are TX and RX. The remaining two wires can be programmed as a
combination of DTR and DSR, or CTS and RTS
in CPCO_CRO(DCS:RDS). DCD and RI are not
available on the 4-wire interface.
21-4
PPC405GP User's Manual
Preliminary