21.3.1
Receiver Buffer Registers (UARTx_RBR)
1
0
71
Figure
21-1. UART Receiver
Buffer
Registers
(UARTx_RBR)
1
0
:
7
I Data bit
Note: UARTx_RBR is shown in standard PowerPC bit notation, where 0 is the MSb and 7 is the LSb.
21.3.2 Transmitter Holding Registers (UARTx_ THR)
1
0
Figure
21-2. UART
Transmitter
Holding
Registers
(UARTx_THR)
1
0
:
7
I Data bit
Note: UARTx_ THR is shown
in
standard PowerPC bit notation, where 0 is the MSb and 7 is the LSb.
21.3.3 Interrupt Enable Registers (UARTx_IER)
Five UART interrupts
on
four priority levels are enabled via the Interrupt Enable Register,
UARTx_IER. Any of the five interrupts can be used to surface a UART interrupt to the PPC405GP
interrupt controller. Each interrupt can
be
enabled by setting its appropriate bit. Resetting
UARTx_IER[4:7]
totally disables the UART interrupt system. Disabling an interrupt prevents it from
being shown as active
in
the UARTx_"R and prevents it from signaling a UART interrupt to the
PPC405G P interrupt controller. See Table 21-3, "Interrupt Priority Level," on page 21-6.
ELSI ERBFI
10
* +
t t
EDSSI ETBEI
Figure
21-3. UART
Interrupt
Enable Registers (UARTx_IER)
0:3
Reserved Always
O.
4
EDSSI Enable Modem Status Interrupt
5
ELSI
Receiver Line Status Interrupt enable
o Enable receiver line status interrupt
1
Disable receiver line status interrupt
Preliminary
Serial Port Operations 21-5
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