IBM PowerPC 405GP User Manual

UIC Masked Status Register (UICO_MSR) ............................................................................................. 10-16
UIC Vector Configuration Register (UICO_VCR) .................................................................................... 10-18
UIC Vector Register (UICO_VR) .............................................................................................................. 10-19
Using the Value in UICO_ VR as a Vector Address or Entry Table Lookup .................... ............. ....... 10-20
Vector Generation Scenarios ............................................................................................................. 10-20
Interrupt Handling in the Processor Core .................................................................................................... 10-22
Architectural Definitions and Behavior .............................................................................. ........................... 10-22
Behavior of the PPC405GP Implementation ............................................................................................... 10-23
Interrupt Handling Priorities ............................................................................................ ............................. 10-24
Critical and Noncritical Interrupts ................................................................................................................. 10-26
General Interrupt Handling Registers ........................................................................................................... 10-27
Machine State Register (MSR) ........................................ ~ ...................................................................... 10-28
Save/Restore
Registers 0 and 1 (SRRO-SRR1) .................................................................................... 10-29
Save/Restore Registers 2 and 3 (SRR2-SRR3) .. ....... ....... ..... ............ ................. ....... ... ............ ............ 10-30
Exception Vector Prefix Register (EVPR) ................... ........................................................................... 10-31
Exception Syndrome Register (ESR) ......................................................................... ............. ................ 10-31
Data Exception Address Register (DEAR) ................................................................. ............................. 10-34
Critical Input Interrupts ................................................................................................................................ 10-34
Machine Check Interrupts ............................................. ............................................................................... 10-35
Instruction Machine Check Handling ...................................................................................................... 10-35
Data Machine Check Handling ................................................................................................................ 10-36
Data
Storage Interrupt ............................................................................................................... ........... ....... 10-36
Instruction Storage Interrupt ................................................................................. :...................................... 10-38
External Interrupt ................................................. ............. ........................................................................... 10-38
External Interrupt Handling ..................................................................................................... ................ 10-39
Alignment Interrupt ......................................................................................................... ........... .................. 10-39
Program Interrupt ........................................................................................................................................ 10-40
System Call Interrupt ................................................................................................................................... 10-41
Programmable Interval Timer (PIT) Interrupt ............................................................................................... 10-41
Fixed Interval Timer (FIT) Interrupt................... ....... ..... ........ ............ ...... ......... .......... ........... ..... .... .... .... ...... 10-42
Watchdog Timer Interrupt ... ..... ........ .................. ...... ............. .......... ..... ............ .... ...... ................ ..... ... ... ....... 10-43
Data TLB Miss Interrupt ............ ... ...... ...................... ......... ..... ............. ....... ...... .... ......... ......... ...... ................ 10-43
Instruction TLB Miss Interrupt ...................................................................................................................... 10-44
Debug Interrupt ............................................................................................................................................ 10-44
Chapter 11. Timer Facilities ................................................................................................ 11-1
Time Base ..................................................................................................................................................... 11-2
Reading the Time Base ....... ....... .... .......... .... ........ .... ......... ....... ...... ...... ...... ..... ..... ....... ......... ..... ...... ......... 11-3
Writing the Time Base ............................................................................................................................... 11-3
Programmable Interval Timer (PIT) ............................................................................................................... 11-4
Fixed Interval Timer (FIT) ......................................................................................................................... 11-5
Watchdog Timer ..... ... .... ..... .... ........... ................. ............ ...... .... ........ .... .............. .... ..... ......... .................... ..... 11-6
Timer Status Register (TSR) ................................ ... ...................................................................................... 11-8
Timer
Control Register (TCR) ....... ... ..... ......... ...... ....... ............. ........ ................. .......... ................ .............. ...... 11-9
Chapter 12. Debugging ........................................................................................................ 12-1
Development Tool Support ............................................................................................................................ 12-1
Debug Interfaces ........................................................................................................................................... 12-1
IEEE 1149.1 Test Access Port (JTAG Debug Port) ...................................................................................... 12-1
JTAG Connector ........ .... ...... ..... .................... .... .......... ........ ..... ...... ....... ..... .... .... ... .......... ................ ....... ........ 12-2
JTAG Instructions ..................................................................................................................................... 12-3
JTAG Boundary Scan ............................................................................................................................... 12-3
JTAG Implementation ................. ............... ... ............. .... ...... ..... .... ... ..... ............ ............. ......... ..... ..... ..... ... 12-4
JTAG 10 Register (CPCO_JTAGID) .......................................................................................................... 12-4
Trace Port...................... ............... ..... .......... ........ ......... ........ ............. ........ .................... .... .......... ... ....... ........ 12-5
Debug Modes .............................................................................................................................. .................. 12-6
Internal Debug Mode ................................................................................................................................ 12-6
x PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English