IBM PowerPC 405GP User Manual

External Debug Mode .......... ..................... ............... ....... ............. ........ ........... ........... .... ......................... ... 12-6
Debug Wait Mode .... .... ....... ....................... ........ ............ ......... ......... .................. .... .... ................ ...... ..... ..... 12-7
Real-time Trace Debug Mode .......... .............. ......... ...... ....... .... .................. .... .............. ........... ...... ............ 12-7
Processor Control .... ...... ....... ... ..... ........ ..... ............ ............. ..................... ........... ........... ........... ....... ...... ... ..... 12-8
Processor Status..... ......... ....... ... ........... ... .... ....... ............ ............ ............. ............. ......... .................... ....... ..... 12-8
Debug Registers ............ ; ................................................................................................................................ 12-8
Debug Control Registers .......... ........................... .... ..... ....................... ........... ............ .................... ...... ..... 12-9
Debug Control Register ° (DBCRO) ...................................................................................................... 12-9
Debug Control Register1 (DBCR1) ..................................................................................................... 12-11
Debug Status Register (DBSR) .............................................................................................................. 12-12
Instruction Address Compare Registers (IAC1-IAC4) ............................................................................ 12-14
Data Address Compare Registers (DAC1-DAC2) ................................................................................ 12-14
Data Value Compare Registers (DVC1-DVC2) ...................................................................................... 12-15
Debug Events .......................................................................................................................................... 12-16
Instruction Complete Debug Event .......................................................................................................... 12-16
Branch Taken Debug Event .................................................................................................................... 12-17
Exception Taken Debug Event ................................................................................................................ 12-17
Trap Taken Debug Event ........................................................................................................................ 12-17
Unconditional Debug Event ........................................................................................... ; ......................... 12-17
lAC Debug Event ..................................................................................................................................... 12-17
lAC Exact Address Compare .............................................................................................................. 12-17
lAC Range Address Compare ............................................................................................................ 12-17
DAC Debug Event ................................................................................................................................... 12-18
DAC Exact Address Compare ............................................................................................................ 12-19
DAC Range Address Compare ........................................................................................................... 12-19
Data Address Compare (DAC) Applied to Cache Instructions ............................................................ 12-20
DAC Applied to String Instructions ...................................................................................................... 12-21
Data Value Compare Debug Event ......................................................................................................... 12-21
Imprecise Debug Event ..................................................... ; ..................................................................... 12-23
Chapter 13. Clock and Power Management ....................................................................... 13-1
CPM Registers ............................................................................................................................................... 13-1
CPM Enable Register (CPCO_ER) ............................................................................................................ 13-3
CPM Force Register (CPCO_FR) .............................................................................................................. 13-3
CPM Status Register (CPCO_SR) ............................................................................................................. 13-3
Chapter 14. Decompression Controller Operation ........................................................... 14-1
Code Compression and Decompression ........... ....... ............................................ ........ ... .......... ......... ........... 14-1
Code Compression .................................................................................................................................... 14-1
Code Decompression .......... ................... ......... ..... ........ ..... .............. ............ ....... ...... ........................ ... ...... 14-2
Instruction Fetches to Compressed Pages ............................................................................................... 14-2
Instruction Fetches to Uncompressed Pages ............................................................................................ 14-3
Performance .............. : ............................................................................................................................... 14-3
Decompression Controller Registers . ................ ....... ........... ........... ............. .... ............. .................... ....... ...... 14-3
Index Table Origin Registers (DCPO_ITORO-DCPO_ITOR3) ................................................................... 14-4
Decompression Address Decode Definition Registers (DCPO_ADDRO-DCPO_ADDR1) ......................... 14-5
Decompression Configuration Register (DCPO_CFG) .............................................................................. 14-5
Decompression Controller ID Register (DCPO_ID) ................................................................................... 14-6 .
Decompression Controller Version Register (DCPO_ VER) ....................................................................... 14-6
Decompression Controller PLB Error Address Register (DCPO_PLBBEAR) ..... ......... ....... .......... .............. 14-7
Decompression Controller Bus Error Address Register (DCPO_MEMBEAR) ........................................... 14-7
Decompression Controller Error Status Register ° (DCPO_ESR) ............................................................. 14-7
Part IV. PPC405GP External Interfaces .............................................................................. IV-1
Chapter 15. SDRAM Controller ........................................................................................... 15-1
Interface Signals ...... ............... ........ .................. ........ ............ .................................. ......... ....... ....... ............. ... 15-1
Accessing SDRAM Registers .. .......... ..... ........... ........ ........ ............. ............. ..... ............................. ...... .... ... ... 15-2
Preliminary
Contents
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IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English