ARM Cortex-A76 Core User Manual

TGE, [27]
Traps general exceptions. If this bit is set, and SCR_EL3.NS is set, then:
• All exceptions that would be routed to EL1 are routed to EL2.
• The SCTLR_EL1.M bit is treated as 0 regardless of its actual state, other than for reading the
bit.
• The HCR_EL2.FMO, IMO, and AMO bits are treated as 1 regardless of their actual state,
other than for reading the bits.
• All virtual interrupts are disabled.
• Any IMPLEMENTATION DEFINED mechanisms for signaling virtual interrupts are disabled.
• An exception return to EL1 is treated as an illegal exception return.
HCR_EL2.TGE must not be cached in a TLB.
When the value of SCR_EL3.NS is 0 the core behaves as if this field is 0 for all purposes other
than a direct read or write access of HCR_EL2.
TID3, [18]
Traps ID group 3 registers. The possible values are:
0 ID group 3 register accesses are not trapped.
1 Reads to ID group 3 registers executed from Non-secure EL1 are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
Configurations
If EL2 is not implemented, this register is RES0 from EL3
RW fields in this register reset to architecturally UNKNOWN values.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.51 HCR_EL2, Hypervisor Configuration Register, EL2
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B2-213
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core