ARM Cortex-A76 Core User Manual

B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
ICC_SRE_EL3 controls whether the System register interface or the memory-mapped interface to the
GIC CPU interface is used for EL3.
Bit field descriptions
ICC_SRE_EL3 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The Security registers functional group.
• The GIC control registers functional group.
31
0
12
3
SRE
DFB
DIB
RES0
4
Enable
Figure B4-7 ICC_SRE_EL3 bit assignments
RES0, [31:4]
Reserved, RES0.
Enable, [3]
Enables lower Exception level access to ICC_SRE_EL1 and ICC_SRE_EL2. The value is:
1 • Secure EL1 accesses to Secure ICC_SRE_EL1 do not trap to EL3.
• EL2 accesses to Non-secure ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to
EL3.
• Non-secure EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
This bit is RAO/WI.
DIB, [2]
Disable IRQ bypass. The possible values are:
0 IRQ bypass enabled.
1 IRQ bypass disabled.
DFB, [1]
Disable FIQ bypass. The possible values are:
0 FIQ bypass enabled.
1 FIQ bypass disabled.
SRE, [0]
System Register Enable. The value is:
1 The System register interface for the current Security state is enabled.
B4 GIC registers
B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core