B4.18 AArch64 virtual interface control system register summary
The following table lists the AArch64 virtual interface control system registers that have IMPLEMENTATION
DEFINED bits.
See the Arm
®
Generic Interrupt Controller Architecture Specification for more information and a
complete list of AArch64 virtual interface control system registers.
Table B4-4 AArch64 virtual interface control system register summary
Name Op0 Op1 CRn CRm Op2 Type Description
ICH_AP0R0_EL1 3 0 12 8 4 RW B4.19 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities
Group 0 Register 0, EL2 on page B4-336
ICH_AP1R0_EL1 3 0 19 9 0 RW B4.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities
Group 1 Register 0, EL2 on page B4-337
ICH_HCR_EL2 3 4 12 11 0 RW B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
on page B4-338
ICH_VTR_EL2 3 4 12 11 1 RO B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control
Register, EL2 on page B4-341
ICH_VMCR_EL2 3 4 12 11 7 RW B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
on page B4-343
B4 GIC registers
B4.18 AArch64 virtual interface control system register summary
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reserved.
B4-335
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